ZL30122GGG2 ZARLINK [Zarlink Semiconductor Inc], ZL30122GGG2 Datasheet
ZL30122GGG2
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ZL30122GGG2 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. Low Jitter Line Card Synchronizer an email to ZL30122GGG ZL30122GGG2 64 Pin CABGA* *Pb Free Tin/Silver/Copper • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz • ...
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Applications TM • AMCs for AdvancedTCA and MicroTCA Systems • Multi-Service Edge Switches or Routers • DSLAM Line Cards • WAN Line Cards • RNC/Mobile Switching Center Line Cards • ADM Line Cards ZL30122 2 Zarlink Semiconductor Inc. Data Sheet ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Description I/O Pin # Name Type Input Reference B1 ref0 I Input References (LVCMOS, Schmitt Trigger). These are input references d A3 ref1 available for synchronizing output clocks. All three input references can be B4 ref2 automatically or manually ...
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I/O Pin # Name Type Status E1 dpll_lock O Lock Indicator (LVCMOS). This is the lock indicator pin for the DPLL. This output goes high when the DPLL’s output is frequency and phase locked to the input reference. H1 dpll_holdover ...
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I/O Pin # Name Type H5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Miscellaneous F5 IC Internal Connection. Leave unconnected Internal Connection. ...
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Functional Description The ZL30122 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety ...
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DPLL Mode Of Operation The DPLL supports three modes of operation - free-run, normal, and holdover. The mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2. Reset No references ...
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Ref and Sync Inputs There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled using a built-in state machine or set in a manual mode.The selected reference input is used to ...
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Each of the ref inputs accept a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz. Built-in frequency detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-defined ...
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Coarse Frequency Monitor (CFM) The CFM block monitors the reference frequency over a measurement period of 30 µs so that it can quickly detect large changes in frequency. A CFM failure (cfm_fail) is triggered when the frequency has changed by ...
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Output Clocks and Frame Pulses The ZL30122 offers a wide variety of outputs including one low-jitter differential LVPECL clock (diff_clk_p/n), one SONET/SDH LVCMOS (sdh_clk) output clock and one programmable LVCMOS (p_clk) output clock. In addition to the clock outputs, ...
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Configurable Input-to-Output and Output-to-Output Delays The ZL30122 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. Both the SONET/SDH APLL and the Programmable Synthesizer can be configured to lead or lag ...
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Software Configuration The ZL30122 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor ...
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Addr Register (Hex) Name 14 detected_sync_0 15 detected_sync_1 16 oor_ctrl_0 17 oor_ctrl_1 18 Reserved 19 Reserved 1A gst_mask 1B Reserved 1C gst_qualif_time 1D dpll_ctrl_0 1E dpll_ctrl_1 1F dpll_modesel 20 dpll_refsel 21 dpll_ref_fail_mask 22 dpll_wait_to_restore 23 dpll_ref_rev_ctrl 24 dpll_ref_pri_ctrl_0 25 dpll_ref_pri_ctrl_1 ...
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Addr Register (Hex) Name 28 dpll_lock_holdover_status 29 Reserved 2A - Reserved 35 Programmable Synthesizer Configuration Registers 36 p_enable 37 p_run 38 p_freq_0 39 p_freq_1 3A p_clk_offset90 3B Reserved 3C Reserved 3D p_offset_fine 3E p_fp_freq 3F p_fp_type 40 p_fp_fine_offset_0 41 p_fp_fine_offset_1 ...
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Addr Register (Hex) Name 54 Reserved 55 sdh_offset_fine 56 sdh_fp_freq 57 sdh_fp_type 58 sdh_fp_fine_offset_0 59 sdh_fp_fine_offset_1 5A sdh_fp_coarse_offset 5B - Reserved 5F 60 diff_clk_ctrl 61 diff_clk_sel 62 Reserved 63 fb_offset_fine 64 reserved 65 ref_freq_mode_0 66 Reserved 67 custA_mult_0 68 custA_mult_1 ...
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Addr Register (Hex) Name 6C custA_cfm_low_1 6D custA_cfm_hi_0 6E custA_cfm_hi_1 6F custA_cfm_cycle 70 custA_div 71 custB_mult_0 72 custB_mult_1 73 custB_scm_low 74 custB_scm_high 75 custB_cfm_low_0 76 custB_cfm_low_1 77 custB_cfm_hi_0 78 custB_cfm_hi_1 79 custB_cfm_cycle 7A custB_div ZL30122 Reset Value Description (Hex) 00 ...
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Addr Register (Hex) Name 7B - Reserved 7F 3.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30122 Reset Value Description (Hex) Table 5 - Register Map (continued) 21 Zarlink ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...