ZL30131GGG ZARLINK [Zarlink Semiconductor Inc], ZL30131GGG Datasheet

ZL30131GGG

Manufacturer Part Number

ZL30131GGG

Description

OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer

Manufacturer

ZARLINK [Zarlink Semiconductor Inc]

Datasheet

1.ZL30131GGG.pdf (11 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ZL30131GGG2

Manufacturer:

CORTINA

Quantity:

Company:

H&T Electronics

Part Number:

ZL30131GGG2

Quantity:

200

Company:

H&T Electronics

Part Number:

ZL30131GGG2

Quantity:

200

Current page: 1 of 11
Download datasheet (233Kb)

Features

•

Synchronizes to standard telecom or Ethernet

backplane clocks and provides jitter filtered output

clocks for SONET/SDH, PDH and Ethernet network

interface cards

Supports the requirements of ITU-T G.8262 for

synchronous Ethernet Equipment slave Clocks

(EEC option 1 and 2)

Two independent DPLLs provides timing for the

transmit path (backplane to line rate) and the

receive path (recovered line rate to backplane)

Synchronizes to telecom reference clocks (2 kHz,

N*8 kHz up to 77.76 MHz, 155.52 MHz) or to

Ethernet reference clocks (25 MHz, 50 MHz,

62.5 MHz, 125 MHz)

Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz,

or 0.1 Hz

Supports automatic hitless reference switching and

short term holdover during loss of reference inputs

Generates standard SONET/SDH clock rates (e.g.,

19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,

622.08 MHz) or Ethernet clock rates (e.g. 25 MHz,

50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for

synchronizing Ethernet PHYs

Programmable output synthesizers (P0, P1)

generate telecom clock frequencies from any

p1_clk0

p1_clk1

sync0

sync1

sync2

ref0

ref1

ref2

ref3

ref4

ref5

ref6

ref7

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

/N1

/N2

Ref Mon

Input

Ports

mode

hold

Figure 1 - Functional Block Diagram

lock

ref_out

Zarlink Semiconductor Inc.

DPLL

•

Applications

•

C/SPI

OC-192/STM-64 SONET/SDH/10GbE

multiple of 8 kHz up to 100 MHz (e.g., T1/E1,

DS3/E3)

Generates several styles of output frame pulses

with selectable pulse width, polarity, and frequency

Configurable input to output delay and output to

output phase alignment

Configurable through a serial interface (SPI or I

DPLLs can be configured to provide synchronous

or asynchronous clock outputs

ITU-T G.8262 Line Cards which support 1GbE and

10GbE interfaces

SONET line cards up to OC-192

SDH line cards up to STM-64

ZL30131GGG

ZL30131GGG2

Network Interface Synchronizer

DPLL

JTAG

osci

*Pb Free Tin/Silver/Copper

Ordering Information

APLL

-40

100 Pin CABGA

100 Pin CABGA*

C to +85

osco

Short Form Data Sheet

ref0

ref7

ZL30131

Trays

diff0_p/n

diff1_p/n

apll_clk0

apll_clk1

p0_clk0

p0_clk1

p0_fp0

p0_fp1

February 2008

Related parts for ZL30131GGG

ZL30131GGG Summary of contents

Page 1

... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2008, Zarlink Semiconductor Inc. All Rights Reserved. OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer ZL30131GGG ZL30131GGG2 *Pb Free Tin/Silver/Copper multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3) • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency • ...

Page 2

Pin Description I/O Pin # Name Type Input Reference C1 ref0 I Input References 7:0 (LVCMOS, Schmitt Trigger). These input references are u B2 ref1 available to both the Tx DPLL and the Rx DPLL for synchronizing output clocks. A3 ...

Page 3

I/O Pin # Name Type J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for ...

Page 4

I/O Pin # Name Type Serial Interface E2 sck_scl I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts ...

Page 5

I/O Pin # Name Type J3 tms I Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of u the TAP controller. This pin is internally pulled then it should be left unconnected. Master Clock ...

Page 6

I/O Pin # Name Type Ground. 0 Volts ...

Page 7

Pin Diagram TOP VIEW sync1 sync2 ref2 B sync0 ref1 ref4 C ref0 mode_0 ref3 D NC mode_1 diff1_en E ref_out sck/ cs_b/ scl asel0 F si/ asel2 asel1 sdh G so int_b NC ...

Page 8

Functional Description The ZL30131 OC-192/STM-64 PDH/SONET/SDH/10GbE Network Interface Synchronizer is a highly integrated device that provides timing for both PDH/SONET/SDH and Ethernet network interface cards. A functional block diagram is shown in Figure 1. This device is ideally suited ...

Page 9

Page 10

For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...

Page 11

Related keywords

ZL30131GGG datasheet
ZL30131GGG data sheet
ZL30131GGG pdf datasheet
ZL30131GGG component
ZL30131GGG part
ZL30131GGG distributor
ZL30131GGG RoHS
ZL30131GGG datasheet download