ZL30407QCC1 ZARLINK [Zarlink Semiconductor Inc], ZL30407QCC1 Datasheet
ZL30407QCC1
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ZL30407QCC1 Summary of contents
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... DS Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. SONET/SDH Network Element PLL Z L30407QCC ZL30407QCC1 Applications • Synchronization for SDH and SONET Network Elements • Clock generation for ST-BUS and GCI backplanes ...
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The ZL30407 operates in NORMAL (LOCKED), HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or ...
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ZL30407 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ZL30407 Pinout 1.1 Pin Connections SECOR OE CS RESET GND IC IC VDD R Figure 2 - Pin Connections for 80-pin LQFP package ZL30407 ...
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Pin Description Pin # Name 1 IC 2-5 A1-A4 6 GND 7-8 A5-A6 9 FCS 10 VDD 11 GND 12 F16o 13 C16o 14 C8o 15 C4o 16 C2o 17 F0o 18 MS1 19 MS2 ZL30407 Description Internal Connection. Leave ...
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Pin Description (continued) Pin # Name 20 F8o 21 E3DS3/OC3 22 E3/DS3 23 SEC 24 PRI 25 GND GND 28 AVDD 29 VDD 30 C155N 31 C155P 32 GND 33 NC ZL30407 Description Frame Pulse ST-BUS/GCI 8.192 ...
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Pin Description (continued) Pin # Name 34 Tdo 35 Tms 36 Tclk 37 Trst 38 Tdi PRIOR 42 C1.5o 43 C6o GND 46 C19o 47 RefSel 48 RefAlign ZL30407 Description IEEE1149.1a Test ...
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Pin Description (continued) Pin # Name 49 VDD C20i 52 GND 53 C34/C44 54 VDD 55 HOLDOVER LOCK SECOR ZL30407 Description Positive Power ...
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Pin Description (continued) Pin # Name 64 RESET 65 HW 66- GND VDD R ZL30407 Description RESET (5 V tolerant ...
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Functional Description The ZL30407 is a Network Element PLL designed to provide timing for SDH and SONET equipment conforming to ITU-T, ANSI, ETSI and Telcordia recommendations. In addition, it generates clocks for legacy PDH equipment operating at DS1, DS2, ...
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Some of the key elements of the Core PLL are shown in Figure 3 "Core PLL Functional Block Diagram". LOCK HOLDOVER RefAlign MUX Figure 3 - Core PLL Functional Block Diagram 2.2.1 Digitally Controlled Oscillator (DCO) The DCO is an ...
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Phase Slope Limiters Phase slope limiting is achieved by clamping the size of the error term from the phase detector. Limiting the size of the error term means that the output clocks move slowly in phase as the PLL ...
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For 1.5 Hz filtering applications (FCS = 0, FCS2 = 0) - Wait until the ZL30407 LOCK indication is high, indicating that it is locked - Pull RefAlign low Hold RefAlign low for 250 µ Pull RefAlign ...
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For 6 Hz and 12 Hz filtering applications (FCS = 1, FCS2 = 1 or FCS = 0, FCS2 = Wait until the ZL30407 LOCK indication is high, indicating that it is locked - Pull RefAlign ...
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Figure 4 - C34/C44, C155o Clock Generation Options All clocks and frame pulses (except the C155) are output with CMOS logic levels. The C155 clock (155.52 MHz) is output in a standard LVDS format. 2.3.2 Output Clocks Phase ...
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MS2,MS1 = 01 OR RefSel change MS2,MS1 = 00 RESET = 1 OR MS2,MS1 = 01 FREE- RESET RUN 10 MS2,MS1 = 10 forces unconditional return from any state to Free-run Notes: {AUTO} - Automatic internal transition {MANUAL} - User ...
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Holdover State (Holdover Mode) The Holdover State is typically entered for short durations while network synchronization is temporarily disrupted. In Holdover Mode, the ZL30407 generates clocks, which are not locked to an external reference signal but their frequencies are ...
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State Transitions In a typical Network Element application, the ZL30407 will most of the time operate in Normal mode (MS2, MS1 == 00) generating synchronous clocks. Its two Acquisition PLLs will continuously monitor the input references for signs of ...
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Microprocessor Interface The ZL30407 can be controlled by a microprocessor ASIC type of device that is connected directly to the hardware control pins. If the HW pin is tied low (see Figure 7 "Hardware and Software ...
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Hardware Control Pins C MS2 O MS1 N T FCS R RefSel O L RefAlign LOCK S T HOLDOVER A T PRIOR U S SECOR Figure 7 - Hardware and Software Control Options 3.1 Hardware Control The Hardware control is ...
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FCS pin: Filter Characteristic Select. The FCS (pin 9) input is used to select the filtering characteristics of the Core PLL. See Table 1, “Loop Filter Selection” on page 13 for details. FCS 0 Filter corner frequency set to 1.5 ...
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In addition to the Control bits shown in Figure 7 "Hardware and Software Control Options", the ZL30407 has a number of bits and registers that are accessed infrequently e.g and 12 Hz PLL loop filter selection, Phase Offset ...
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Register Description Address Bit Name 7 RefSel Reference Select. A zero selects the PRI (Primary) reference source as the input reference signal and a one selects the SEC (secondary) reference. 6-5 RSV Reserved 4-3 MS2, MS1 Mode ...
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Address Bit Name 7 PRIOR Primary Reference Out of Range. This output goes high when: the primary reference is off its nominal frequency by more than ±12 ppm. The • frequency offset monitor updates internally every 10 sec ...
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C20i Clock Accuracy 0 ppm +4.6 ppm -4.6 ppm -16.6 -13.8 -20 Figure 8 - Primary and Secondary Reference Out of Range Thresholds Address Bit Name 7 E3DS3/OC3 E3, DS3 or OC-3 clock select. Setting this bit to ...
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Address Bit Name 7-4 RSV Reserved 3 OffEn Offset Enable. Set high to enable programmable phase offset adjustment (C16 Phase Offset Adjustment and C1.5 Phase Offset Adjustment) between the input reference and the generated clocks ...
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Address Bit Name 7 RSV Reserved 6 RSV Reserved 5-3 C1.5POA2 C1.5 Phase Offset Adjustment. These three bits allow for changing of to the phase offset of the C1.5o clock relative to the active input reference. C1.5POA0 The ...
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Address Bit Name 7-5 RSV Reserved 4 F8odis F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns active high framing pulse output. 3 F0odis F0o Frame Pulse Disable. When set high, this ...
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Address Bit Name 7-0 FPOA7 - 0 Fine Phase Offset Adjustment. This register allows phase offset adjustment of all output clocks and frame pulses (C16o, C8o, C4o, C2o, F16o, F8o, F0o, C155, C19o, C34/44, C1.5o, C6o) relative to ...
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Address Bit Name 7-5 RSV Reserved 4-3 InpFreq1-0 Input Frequency. These two bits identify the Secondary Reference Clock frequency 19.44 MHz - kHz - 10 = 1.544 MHz - 11 = 2.048 ...
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Address Bit Name 7-0 MCFC7 - 0 Master Clock Frequency Calibration. This byte contains bit 7 to bit 0 of the Master Clock Frequency Calibration Register. Table 22 - Master Clock Frequency Calibration Register 1 (R/W) 4.0 Applications ...
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System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL The FREE-RUN to HOLDOVER to NORMAL transition represents a sequence of steps that will most likely occur during a new system installation or scheduled maintenance of timing cards. The process starts ...
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Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses its single reference clock unexpectedly. The sequence starts with the reference clock transitioning from OK ...
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Single 8 kHz Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of the 8 kHz reference. The failure conditions triggering ...
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Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL The NORMAL to AUTO-HOLDOVER to HOLDOVER to NORMAL sequence represents the most likely operation of ZL30407 in Network Equipment. The sequence starts from the Normal state and transitions to ...
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Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL The NORMAL to HOLDOVER to NORMAL mode switching is usually performed when: • A reference clock is available but its frequency drifts beyond some specified limit Network Element with ...
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Master/Slave Timing Protection Switching Carrier Class Telecommunications Equipment deployed in today’s networks guarantee better than 99.999% operational availability (equivalent to less than 7 minutes of downtime per year). This high level of uninterrupted service is achieved by fully redundant ...
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Programming Master Clock Oscillator Frequency Calibration Register The Master Crystal Oscillator and its programmable Master Clock Frequency Calibration register (see Table 19, Table 20, Table 21, and Table 22) are described in Section 2.5 "Master Clock Frequency Calibration Circuit", ...
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Characteristics 5.1 AC and DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Supply voltage 2 Voltage on any pin 3 Current on any pin 4 Storage temperature 5 Package power dissipation (80 pin LQFP) 6 ESD rating * Voltages ...
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AC Electrical Characteristics - Timing Parameter Measurement - CMOS Voltage Levels* Characteristics 1 Threshold voltage 2 Rise and fall threshold voltage High 3 Rise and fall threshold voltage Low * Voltages are with respect to ground (GND) unless otherwise stated. ...
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AC Electrical Characteristics - Microprocessor Timing* Characteristics 1 DS Low 2 DS High 3 CS Setup 4 CS-Hold 5 R/W Setup 6 R/W Hold 7 Address Setup 8 Address Hold 9 Data Read Delay 10 Data Read Hold 11 Data ...
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AC Electrical Characteristics - ST-BUS and GCI Output Timing* Characteristics 1 F16o pulse width low (nom 61 ns) 2 F8o to F16o delay 3 C16o pulse width low 4 F8o to C16o delay 5 F8o pulse width high (nom 122 ...
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AC Electrical Characteristics - DS1 and DS2 Clock Timing* Characteristics 1 C6o pulse width low 2 F8o to C6o delay 3 C1.5o pulse width low 4 F8o to C1.5o delay * Supply voltage and operating temperature are as per Recommended ...
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AC Electrical Characteristics - C155o and C19o Clock Timing Characteristics 1 C155o pulse width low 2 C155o to C19o rising edge delay 3 C155o to C19o falling edge delay 4 C19 pulse width high * Supply voltage and operating temperature ...
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AC Electrical Characteristics - Input to Output Phase Offset (after phase realignment)* Characteristics 1 8 kHz ref: pulse width high or low 2 8 kHz ref input to F8o delay 3 1.544 MHz ref: pulse width high or low 4 ...
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AC Electrical Characteristics - Input Control Signals* Characteristics 1 Input controls Setup time 2 Input controls Hold time * Supply voltage and operating temperature are as per Recommended Operating Conditions F8o MS1, MS2 RefSel, FCS, RefAlign E3/DS3 E3DS3/OC3 Figure 22 ...
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Performance Characteristics Performance Characteristics* Characteristics 1 Holdover accuracy 2 Holdover accuracy 3 Holdover accuracy 4 Holdover accuracy 5 Holdover stability 6 Capture range 7 Reference Out of Range Threshold Lock Time Filter 9 ...
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Performance Characteristics* (continued) Characteristics Filter Filter * Supply voltage and operating temperature are as per Recommended Operating Conditions. Note: See Section 2.2.3 for an explanation of Phase Slope Limiting. Performance Characteristics : Measured Output ...
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Performance Characteristics : Measured Output Jitter - G.747 conformance ITU-T G.747 Jitter Generation Requirements Jitter Network Measurement Interface Filter 1 DS2 kHz 6312 kbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. ...
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Performance Characteristics : Measured Output Jitter - G.751 conformance ITU-T G.751 Jitter Generation Requirements Jitter Network Measurement Interface Filter 1 E3 100 Hz to 800 kHz 34368 kbps * Supply voltage and operating temperature are as per Recommended Operating Conditions. ...
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Performance Characteristics : Measured Output Jitter - G.813 conformance (Option 1 and Option 2) ITU-T G.813 Jitter Generation Requirements Jitter Interface Measurement Filter Option 1 1 STM-1 65 kHz to 1.3 MHz 155.52 Mbps 2 500 Hz to 1.3 MHz ...
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Performance Characteristics : Measured Output Jitter - EN 300 462-7-1 conformance ETSI EN 300 462-7-1 Jitter Generation Requirements Jitter Interface Measurement Filter 1 STM-1 65k Hz to 1.3 MHz optical 2 500 Hz to 1.3 MHz 155.52 Mbps 3 STM-1 ...
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Performance Characteristics - Measured Output Jitter - Unfiltered* Characteristics 1 C1.5o (1.544 MHz) 2 C2o (2.048 MHz) 3 C4o (4.096 MHz) 4 C6o (6.312 MHz) 5 C8o (8.192 MHz) 6 C8.5o (8.592 MHz) 7 C11o (11.184 MHz) 8 C16o (16.384 ...
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