ZL30410QCG1 ZARLINK [Zarlink Semiconductor Inc], ZL30410QCG1 Datasheet - Page 7

• Manufacturer Part Number: ZL30410QCG1
• Description: Multi-service Line Card PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
Pin #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
E3DS3/OC3
E3/DS3
C155N
C155P
Name
AVDD
GND
GND
GND
SEC
VDD
Tms
PRI
Tdo
NC
IC
E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin
enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155
clock outputs (high impedance) and sets C34/C44 output to provide C34 and
C44 clocks.
E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin
is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44
output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set
low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and
logic high selects 8.592 MHz clock.
Secondary Reference (Input). This input is used as a secondary reference
source for synchronization. The ZL30410 can synchronize to the falling edge
of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the
19.44 MHz clock. In Hardware Control, selection of the input reference is
based upon the RefSel control input. This pin is internally pulled up to VDD.
Primary Reference (Input). This input is used as a primary reference source
for synchronization. The ZL30410 can synchronize to the falling edge of the
8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz
clock. In Hardware Control, selection of the input reference is based upon the
RefSel control input. This pin is internally pulled up to VDD.
Ground
Internal Connection. Leave unconnected.
Ground
Positive Analog Power Supply. Connect this pin to VDD.
Positive Power Supply.
Clock 155.52 MHz (LVDS output). Differential outputs for the 155.52 MHz
clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or
they can be disabled by applying logic high. In the disabled state the LVDS
outputs are internally terminated with an integrated 100 Ω resistor (two 50Ω
resistors connected in series). The middle point of these resistors is internally
biased from a 1.25 V LVDS bias source.
Ground
No internal bonding Connection. Leave unconnected.
IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on
this pin on the falling edge of Tclk clock. If not used, this pin should be left
unconnected.
IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the
state transition on the TAP controller. This pin is internally pulled up to VDD. If
not used, this pin should be left unconnected.
Zarlink Semiconductor Inc.
ZL30410
7
Description
Data Sheet