ZL50063GAC ZARLINK [Zarlink Semiconductor Inc], ZL50063GAC Datasheet - Page 19

• Manufacturer Part Number: ZL50063GAC
• Description: 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (32Mbps), and 32 Inputs and 32 Output
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.5
Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different
frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate
20ns of jitter of 10kHz frequency may only be able to tolerate 10ns of jitter of 1MHz frequency. Therefore, jitter
tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the
carrier frequency. In the case of the ZL50063, the input clock is 8.192MHz, and the jitter associated with this clock
can have the highest frequency component at 4.096MHz.
For the above reasons, jitter tolerance of the ZL50063 has been characterized at 32.768Mbps. Tolerance of jitter of
different frequencies are shown in the “AC Electrical Characteristics“ section, table “Input Clock Jitter Tolerance“ on
page 55. The Jitter Tolerance Improvement Circuit was enabled (Control Register, bit FBDEN set HIGH, and bits
FBD_MODE[2:0] set to 111
3.0
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
3.1
Control of the Input Bit Delay allows each input stream to have a different frame boundary with respect to the
master frame pulse, FP8i. Each input stream can be individually delayed by up to 7 3/4 bits with a resolution of 1/4
bit of the bit period.
3.1.1
Input Bit Delay Registers LIDR0 - 15 and BIDR0 - 15 work in conjunction with the SMPL_MODE bit in the Control
Register to allow users to control input bit fractional delay as well as input bit sample point selection for greater
flexibility when designing switch matrices for high speed operation.
When SMPL_MODE = LOW (input bit fractional delay mode), bits LID[4:0] and BID[4:0] in the LIDR0 - 15 and
BIDR0 - 15 registers respectively define the input bit fractional delay of the corresponding local and backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.
Refer to Figure 8 for Input Bit Delay Timing at 32Mbps data rates.
Refer to Figure 9 for Input Sampling Point Selection Timing at 32Mbps data rates.
Input Clock Jitter Tolerance
Input Offsets
Input and Output Offset Programming
Input Bit Delay Programming (Backplane and Local Input Streams)
B
), and the sampling point was optimized.
Zarlink Semiconductor Inc.
ZL50063
19
Data Sheet