ZL50075GAC ZARLINK [Zarlink Semiconductor Inc], ZL50075GAC Datasheet - Page 10

• Manufacturer Part Number: ZL50075GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
A6, A7, D9, B9, C9, A8, A9,
A10, B10, C10, A11, D11,
C11, B11, A12, D12, A13,
A1, A2, C6, D6,
B3, B4, C7, B5,
B6, B7, A3, A4,
A5, D7, B8, C8
U13, V12
B12, A14
D2, U4
E4, V2
T10
Pin
K1
CK_SEL0-1 TDM Master Clock Input Select
CKo0-1
FPo0-1
Name
D15-0
A18-0
ODE
FPi0
Microprocessor Port and Reset
ST-BUS/GCI-Bus Frame Pulse Input (5 V Tolerant Input)
This pin accepts the 8 kHz frame pulse which marks the frame
boundary of the TDM data streams. The pulse width is nominally
one CKi0 clock period (assuming ST-BUS mode) selected by the
CK_SEL1-0 inputs. The active state of the frame pulse may be
either high or low, programmed by the Input Clock Control Register
(Section 14.5).
ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate
Control)
These clock outputs can be programmed to generate 8.192 MHz,
16.384 MHz, 32.678 MHz or 65.536 MHz TDM clock outputs. The
active edge can be programmed to be either rising or falling. The
source of the clock outputs can be derived from either the CKi0
inputs or the internal system clock. The frequency, active edge and
source of each clock output can be programmed independently by
the Output Clock Control Register (Section 14.6). For 65.536 MHz
output clock, the total loading on the output should not be larger
than 10pF.
ST-BUS/GCI-Bus Frame Pulse Outputs (3.3 V Outputs with
Slew-Rate Control)
These 8 kHz output pulses mark the frame boundary of the TDM
data streams. The pulse width is nominally one clock period of the
corresponding CKo output. The active state of each frame pulse
may be either high or low, independently programmed by the
Output Clock Control Register (Section 14.6).
Inputs used to select the frequency and frame alignment of CKi0
and FPi0:
CK_SEL1 = 0, CK_SEL0 = 0, 8.192 MHz
CK_SEL1 = 0, CK_SEL0 = 1, 16.384 MHz
CK_SEL1 = 1, CK_SEL0 = 0, 32.768 MHz
CK_SEL1 = 1, CK_SEL0 = 1, 65.536 MHz
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
This is the asynchronous output enable control for the output
streams. When it is high, the streams are enabled. When it is low,
the output streams are tristated.
Microprocessor Port Data Bus (5 V Tolerant Bi-directional with
Slew-Rate Output Control)
16 bit bi-directional data bus. Used for microprocessor access to
internal memories and registers.
Microprocessor Port Address Bus (5 V Tolerant Inputs)
19 bit address bus for the internal memories and registers. Note A0
is not used and should be connected to a defined logic level.
Zarlink Semiconductor Inc.
ZL50075
10
Description
Data Sheet