EM25LV010-25KGBS EMC [ELAN Microelectronics Corp], EM25LV010-25KGBS Datasheet - Page 16

• Manufacturer Part Number: EM25LV010-25KGBS
• Description: 1 Megabit (128K x 8) Serial Flash Memory
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
The instruction sequence is shown in Figure 18. The Chip Select (S#) must be driven High
after the eighth bit of the instruction code has been latched in, otherwise, the Chip Erase
instruction will not execute. As soon as Chip Select (S#) is driven High, the self-timed Chip
Erase cycle (whose duration is tBE) is initiated. While the Chip Erase cycle is in progress, the
Status Register may be read to check the value of the (BUSY) bit. The (BUSY) bit is “1”
during the self-timed Chip Erase cycle, and is “0” when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is executed only if both Block Protect (BP1, BP0) bits are set
at “0”. The Chip Erase (CE) instruction is ignored if one or more blocks are protected.
Deep Power-Down (DP)
Executing the Deep Power-Down (DP) instruction is the only way to put the device in the
lowest power consumption mode (the Deep Power-Down mode). It can also be used as an
extra software protection mechanism because in this mode, the device ignores all Write,
Program, and Erase instructions.
Driving Chip Select (S#) High will deselect the device, and put the device in Standby mode (if
there is no internal cycle currently in progress). Note that this is not the Deep Power-Down
mode. Deep Power-down mode can only be entered by executing the Deep Power-Down
(DP) instruction which reduces the standby current from ICC1 to ICC2 as specified in Table
13.
Once the device has entered the Deep Power-Down mode, all instructions are ignored except
for the Release from Deep Power-Down and Read Electronic Signature (RES) instruction.
This releases the device from this mode. The Release from Deep Power-Down (RES) and
Read Device ID instruction also allows the ID of the device to be output through Serial Data
Output (Q).
The Deep Power-Down mode automatically stops at Power-down, and the device always
powers up in the Standby mode.
The Deep Power-Down (DP) instruction is entered by driving Chip Select (S#) Low, followed
by the instruction code on Serial Data Input (D). Chip Select (S#) must be driven Low for the
entire duration of the sequence. The instruction sequence is shown in Figure 19.
Chip Select (S#) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction will not be executed. As soon as
Chip Select (S#) is driven High, it requires a delay of tDP before the supply current is reduced
to ICC2 and the Deep Power-Down mode is entered. Any Deep Power-Down (DP)
instruction executed while an Erase, Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
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This specification is subject to change without further notice. (11.08.2004 V1.0)