SI1030-A-GM Silicon Laboratories Inc, SI1030-A-GM Datasheet

SI1030-A-GM

Manufacturer Part Number

SI1030-A-GM

Description

Manufacturer

Silicon Laboratories Inc

Datasheets

1.SI1020-A-GM.pdf (538 pages)

2.SI1020-A-GM.pdf (538 pages)

3.SI1030-A-GM.pdf (2 pages)

Specifications of SI1030-A-GM

Lead_time

Pack_quantity

480

Comm_code

85423190

Current page: 1 of 2
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Ultra-Low Power @ 3.6 V

12-Bit; 16 ch. Analog to Digital Converter

Two Low Current Comparators

Internal 6-Bit Current Reference

Metering-Specific Peripherals

EZRadioPRO

Wireless MCU

110 µA/MHz IBAT; DC-DC enabled

110 nA sleep current with data retention; POR monitor enabled

400 nA sleep current with smaRTClock (internal LFO)

700 nA sleep current with smaRTClock (external XTAL)

2 µs wake-up from any sleep mode

Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode

External pin or internal VREF (no external capacitor required)

On-chip PGA allows measuring voltages up to twice the 

reference voltage

Autonomous burst mode with 16-bit automatic averaging 

accumulator

Integrated temperature sensor

Programmable hysteresis and response time

Configurable as interrupt or reset source

Up to ±500 µA; source and sink capability

Enhanced resolution via PWM interpolation

DC-DC buck converter allows dynamic voltage scaling for 

maximum efficiency (250 mW output)

Sleep-mode pulse accumulator with programmable switch 

de-bounce and pull-up control interfaces directly to metering sensor

Dedicated Packet Processing Engine (DPPE) includes hardware AES,

DMA, CRC, and encoding blocks for acceleration of wireless protocols

Manchester and 3 out of 6 encoder hardware for power efficient imple-

mentation of the wireless M-bus specification

Frequency range = 240–960 MHz

Sensitivity = –121 dBm

FSK, GFSK, and OOK modulation

Max output power = +20 dBm (Si1020/1/2/3), +13 dBm (Si1024/25/26/

27)

Transceiver

C2CK/RST

VBATDC

GNDDC

VBAT

VDC

GND

IND

DC/DC Buck

Converter

Programming

VBAT

C2D

Reset/PMU

Power On

Hardware

Debug /

XTAL1

XTAL2

XTAL3

XTAL4

VDD

Wake

Reset

VREG

smaRTClock

Low Power

8192/4096 Byte XRAM

24.5 MHz

Enhanced

Precision

Oscillator

External

20 MHz

Controller Core

System Clock

128/64/32/16 kByte

ISP Flash Program

Circuit

Configuration

Analog

CIP-51 8051

256 Byte SRAM

Power

Digital

Power

Memory

Integrated 240–960 MHz EZRadioPRO

SYSCLK

Engine

Encoder

DMA

CRC

AES

SFR

Bus

Ultra Low Power, 128/64/32/16 kB MCU with

High-Speed 8051 µC Core

Memory

Digital Peripherals

Clock Sources

On-Chip Debug

Packages

Internal

Digital Peripherals

VREF

Port I/O Configuration

Timers

0/1/2/3

SMBus

CP1, CP1A

UART

PCA/

WDT

SPI 0

Analog Peripherals

EZRadioPro SPI 1

12-bit

75ksps

ADC

Crossbar Control

Pulse Counter

CP0, CP0A

RF power consumption

Pipelined instruction architecture; executes 70% of instructions in 1 or

2 system clocks

Up to 128 kB Flash; In-system programmable; Full read/write/erase

functionality over the entire supply range

Up to 8 kB data retention RAM

53 port I/O; All 5 V tolerant with high sink 

current and programmable drive strength

Hardware SMBus™ (I2C™ compatible), 2 x SPI™, and UART serial

ports available concurrently

Four general-purpose 16-bit counter/timers

Programmable 16-bit counter/timer array with six capture/compare mod-

ules and watchdog timer

Precision internal oscillators: 24.5 MHz with ±2% accuracy supports

UART operation; spread-spectrum mode for reduced EMI

Low power internal oscillator: 20 MHz

External oscillator: Crystal, RC, C, CMOS clock

smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal LFO with

three independent alarms

On-chip debug circuitry facilitates full speed, non-intrusive in-system

debug (no emulator required)

Provides 4 breakpoints, single stepping

–85 pin LGA (6 x 8 mm)

External

EMIF

VREF

Comparators

18.5 mA receive

18 mA @ +1 dBm transmit

30 mA @ +13 dBm transmit

85 mA @ +20 dBm transmit

Data rate = 0.123 to 256 kbps

Auto-frequency calibration (AFC)

Antenna diversity and transmit/receive switch control

Programmable packet handler

TX and RX 64-byte FIFOs

Frequency hopping capability

On-chip crystal tuning

Crossbar

Decoder

Priority

VDD

VREF

GND

Sensor

Temp

Port 0-1

Port 3-6

Drivers

(240-960 MHz,

Port 2

Port 7

Driver

+20/+13 dBm)

RF XCVR

VCO

AGC

Modulator

Modem

30 MHz

Digital

Sigma

Digital

Delta

Logic

LNA

Mixer

PGA

ADC

P0.0...P1.7

P2.4...P2.7

P3.0...P6.7

P7.0/C2D

RXp

RXn

SDN

nIRQ

GPIOx

XOUT

XIN

Transceiver

Si103x

11.10.11

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