SI51211-A01AFM Silicon Laboratories Inc, SI51211-A01AFM Datasheet

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SI51211-A01AFM

Manufacturer Part Number
SI51211-A01AFM
Description
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI51211-A01AFM

Lead_time
56
Pack_quantity
1
Comm_code
85423990
T
G
Features
Applications
Description
The factory programmable Si51211 is a low power, small footprint and
frequency flexible programmable clock generator targeting low power, low
cost and high volume consumer and embedded applications. The device
operates from a single crystal or an external clock source and generates
1 to 3 outputs up to 200 MHz. They are factory programmed to provide
customized output frequencies, control inputs and ac parameter tuning
like output drive strength that are optimized for customer board condition
and application requirements. A separate VDDO supply pin supports
clock output at a different voltage level.
Functional Block Diagram
Preliminary Rev. 0.7 1/12
HREE
Generates up to 3 CMOS clock
outputs from 3 to 200 MHz
Accepts crystal or reference
clock input


Programmable FSEL, SSEL,
SSON, PD, and OE input
functions
Low power dissipation
Crystal/XO replacement
EMI reduction
Portable devices
EN ERA TO R
CLKIN
XOUT
VDD0
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
3 to 166 MHz reference clock input
VDD
8 to 48 MHz crystal input
XIN/
VSS
3
2
8
1
5
To Pin 7
O
V-REG
UTPUTS
To Pin 4 and Pin 6
To Core
Programmable
Configuration
Modulation
F
Register
PLL with
Control
Copyright © 2012 by Silicon Laboratories
ACTORY
Separate voltage supply pins


0.25% to 1.0% Spread Spectrum
(Center Spread)
Low cycle-cycle jitter
Programmable output rise and
fall times
Ultra small 8-pin TDFN package
(1.4 x 1.6 mm)
Digital still camera
IP phone
Smart meter
V
V
DD
DDO
= 2.5 to 3.3 V
= 1.8 to 3.3 V (V
Dividers,
Buffers,
Switch
Matrix
and
P
R O GRA MM A B LE
6
7 SSCLK3 (VDD0)
4
SSCLK1/
REFCLK/
0E2/FSEL/
SSEL/SS0N
SSCLK2/
REFCLK_D
0E1/FSEL/
SSEL/SS0N/PD
DDO
V
DD
)
Patents pending
FSEL/SSEL/SSON/
SSCLK1/REFCLK
XIN/CLKIN
Ordering Information:
XOUT
VDD
OE2
Pin Assignments
S i 5 1 2 11
C
2
3
4
See page 9.
1
LOCK
Si51211
8
7
6
5
VDDO
SSCLK3
SSCLK2/REFCLK_D
FSEL/SSEL/SSON/
PD/OE1
VSS
Si51211

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