SI5330A-A00200-GMR Silicon Laboratories Inc, SI5330A-A00200-GMR Datasheet
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SI5330A-A00200-GMR
Manufacturer Part Number
SI5330A-A00200-GMR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5330A-A00200-GMR.pdf
(20 pages)
Specifications of SI5330A-A00200-GMR
Lead_time
56
Pack_quantity
1000
Comm_code
85423990
1 . 8 / 2 . 5 / 3 . 3 V L
C
Features
Applications
Functional Block Diagram
Rev. 1.0 4/12
L O C K
Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation
Wide frequency range
Additive jitter: 150 fs RMS typ
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
Single-ended
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz
Differential
or
B
U F F E R
OEB
LOS
IN
Si5330
/ L
O W
Control
E V E L
V
- J
Copyright © 2012 by Silicon Laboratories
DD
I T T E R
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
Small size: 24-lead, 4 x 4 mm
QFN
–40 to +85
T
R A N S L A T O R
V
CLK0
V
CLK1
CLK2
V
CLK3
V
, L
DDO0
DDO1
DDO2
DDO3
°
C
O W
Single-ended
Differential
- S
or
K EW
RSVD_GND
RSVD_GND
RSVD_GND
IN3
IN1
IN2
Ordering Information:
Pin Assignments
See page 14.
24
7
Si5330
23
8
22
9
GND
GND
21
10
20
11
19
12
Si5330
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B