A6810SAT Allegro Micro Systems, Inc., A6810SAT Datasheet

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A6810SAT

Manufacturer Part Number
A6810SAT
Description
Manufacturer
Allegro Micro Systems, Inc.
Datasheet

Specifications of A6810SAT

Date_code
08+

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A6810SAT
Manufacturer:
ALLEGRO
Quantity:
6
Price:
1.00 USD
GROUND
STROBE
SUPPLY
Logic Supply Voltage, V
Driver Supply Voltage, V
Continuous Output Current Range,
Input Voltage Range,
Package Power Dissipation,
Operating Temperature Range, T
Storage Temperature Range,
Caution: These CMOS devices have input
static protection (Class 2) but are still sus-
ceptible to damage if exposed to extremely
high static electrical charges.
CLOCK
LOGIC
ABSOLUTE MAXIMUM RATINGS
OUT
OUT
OUT
OUT
OUT
I
V
P
(Suffi x ‘E–’) ................... -40°C to +85°C
(Suffi x ‘K–’) ................. -40°C to +125°C
(Suffi x ‘S–’) ................... -20°C to +85°C
T
8
7
6
4
5
OUT
S
IN
D
1
2
3
4
5
6
7
8
9
....................................... See Graph
............................... -55°C to +125°C
....................... -0.3 V to V
........................ -40 mA to +15 mA
ST
CLK
V
DD
at T
A6810xA
REGISTER
LATCHES
REGISTER
LATCHES
A
= 25°C
DD
BB
.................. 7.0 V
................... 60 V
BLNK
V
BB
A
14
18
17
16
15
13
12
11
0 1
DD
SERIAL
DATA OUT
SERIAL
DATA IN
BLANKING
OUT
OUT
LOAD
SUPPLY
OUT
OUT
OUT
Dwg. PP-029
+ 0.3 V
1
9
10
2
3
6810
pa ny ing data latches and control cir cuit ry with bipolar sourcing out puts
and pnp active pull downs. De signed pri mar ily to drive vacuum-fl u o -
res cent displays, the 60 V and -40 mA output ratings also allow these
devices to be used in many other peripheral power driver ap pli ca tions.
The A6810– feature an increased data input rate (com pared with the
older UCN/UCQ5810-F) and a con trolled output slew rate.
microprocessor-based systems. With a 3.3 V or 5 V logic supply, serial-
data input rates of at least 10 MHz .
ca tions re quir ing additional drive lines. Similar devices are available as
the A6812– (20 bits) and A6818– (32 bits).
sourcing up to 40 mA. The controlled output slew rate reduces elec tro -
mag net ic noise, which is an important consideration in systems that in-
clude telecommunications and/or microprocessors and to meet govern-
ment emissions regulations. For inter-digit blanking, all output drivers
can be dis abled and all sink drivers turned on with a BLANK ING input
high. The pnp active pull-downs will sink at least
2.5 mA.
per for mance in commercial (suffi x S-), industrial (suffi x E-), or au-
tomtoive (suffi x K–) ap pli ca tions. They are provided in two package
styles for through-hole DIP (suffi x -A) or minimum-area surface-mount
SOIC (suffi x -LW). Copper lead frames, low logic-power dis si pa tion,
and low output-saturation voltages allow all devices to source 25 mA
from all outputs continuously over the max i mum operating tem pera ture
range.
leadframe plating.
FEATURES
■ Controlled Output Slew Rate
■ High-Speed Data Storage
■ 60 V Minimum Output Breakdown
■ High Data Input Rate
■ PNP Active Pull-Downs
■ Low Output-Saturation Voltages
■ Low-Power CMOS Logic and Latches
■ Improved Replacements for TL4810–, UCN5810–, and UCQ5810–
The A6810– devices combine 10-bit CMOS shift registers, ac com -
The CMOS shift register and latches allow direct interfacing with
A CMOS serial data output permits cascade con nec tions in ap pli -
The A6810– output source drivers are npn Dar ling tons, capable of
The A6810– are available in three temperature ranges for op ti mum
The lead (Pb) free versions are provided with 100% matte tin
DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER

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