A2F500M3G-1FGG484 Actel, A2F500M3G-1FGG484 Datasheet

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A2F500M3G-1FGG484

Manufacturer Part Number
A2F500M3G-1FGG484
Description
BGA 484/IC,FPGA,11520-CELL,CMOS
Manufacturer
Actel
Datasheet

Specifications of A2F500M3G-1FGG484

Lead_time
84
Pack_quantity
60
Comm_code
85423990

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A2F500M3G-1FGG484
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-1FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
September 2010
© 2010 Actel Corporation
Actel’s SmartFusion Intelligent Mixed Signal FPGAs
Microcontroller Subsystem (MSS)
High-Performance FPGA
1 Theoretical maximum
2 A2F200 and larger devices
Hard 100 MHz 32-Bit ARM
– 1.25 DMIPS/MHz Throughput from Zero Wait State
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
10/100 Ethernet MAC with RMII Interface
Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
Two I
Two 16550 Compatible UARTs
Two SPI Peripherals
Two 32-Bit Timers
32-Bit Watchdog Timer
8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
– 100 MHz Embedded RC Oscillator; 1% Accurate
– Embedded Analog PLL with 4 Output Phases (0, 90,
Based on Actel's proven ProASIC
Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
Nonvolatile, Live at Power-Up, Retains Program When
Powered Off
350 MHz System Performance
Embedded SRAMs and FIFOs
– Variable Aspect Ratio 4,608-Bit SRAM Blocks
– x1, x2, x4, x9, and x18 Organizations
– True Dual-Port SRAM (excluding x18)
Memory
wires), and Single Wire Viewer (SWV) Interfaces
Kbytes to 512 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
Bandwidth,
Real-Time Counter (RTC)
180, 270)
2
C Peripherals
1
Allowing Multi-Master Schemes
®
Cortex™-M3
®
3 FPGA Fabric
2
Programmable Analog
Analog Front-End (AFE)
Analog Compute Engine (ACE)
I/Os and Operating Voltage
– Programmable Embedded FIFO Control Logic
Secure ISP with 128-Bit AES via JTAG
FlashLock
Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75 to
Up to Three 12-Bit SAR ADCs
– 500 Ksps in 12-Bit Mode
– 550 Ksps in 10-Bit Mode
– 600 Ksps in 8-Bit Mode
Internal 2.56 V Reference or Optional External
Reference
One First-Order ΣΔ DAC (sigma-delta) per ADC
– 12-Bit 500 Ksps Update Rate
Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
– Two High-Voltage Bipolar Voltage Monitors (with 4
– High Gain Current Monitor, Differential Gain = 50, up
– Temperature Monitor (Resolution = ¼°C in 12-Bit
Up
(t
Offloads
Initialization and Processing of ADC, DAC, and SCBs
Sample Sequence Engine for ADC and DAC Parameter
Set-Up
Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
Easily Configured via GUI in Libero
(IDE) Software
FPGA I/Os
– LVDS, PCI, PCI-X, up to 24 mA I
– Up to 350 MHz
MSS I/Os
– Schmitt Trigger, up to 6 mA I
– Up to 180 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
pd
350 MHz
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
to 14 V Common Mode
Mode; Accurate from –55°C to 150°C)
= 15 ns)
to
®
Ten
Cortex-M3–Based
to Secure FPGA Contents
High-Speed
OH
Voltage
MSS
, 8 mA I
®
OH
Integrated Design
/I
OL
from
OL
Revision 3
Comparators
Analog
I

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