A3P030-VQG100I Actel, A3P030-VQG100I Datasheet

A3P030-VQG100I

Manufacturer Part Number

A3P030-VQG100I

Description

A3P030-VQG100I

Manufacturer

Actel

Datasheet

1.A3P030-VQG100I.pdf (180 pages)

Specifications of A3P030-VQG100I

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Comm_code

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ProASIC3 Flash Family FPGAs

Features and Benefits

High Capacity

Reprogrammable Flash Technology

On-Chip User Nonvolatile Memory

Performance

In-System Programming (ISP) and Security

Low Power

High-Performance Routing Hierarchy

Table 1 •

January 2005

System Gates

VersaTiles (D-Flip-Flops)

RAM kbits (1,024 bits)

4,608 Bit Blocks

FlashROM (FROM) Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. Six chip (main) and three quadrant global networks are available for A3P060 and above.

2. For higher densities and support of additional features, refer to the

QFN

VQFP

TQFP

PQFP

FBGA

•

30 k to 1 Million System Gates

Up to 144 kbits of True Dual-Port SRAM

Up to 288 User I/Os

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

Live-At-Power-Up Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

1 kbit of FlashROM (FROM)

150+ MHz Internal System Performance with 3.3 V,

66 MHz 64-bit PCI (except A3P030)

Up to 350 MHz External System Performance

Secure ISP Using On-Chip 128-Bit AES Decryption via

JTAG (IEEE1532-compliant) (except A3P030)

FlashLock™ to Secure FPGA Contents

1.5 V Core Voltage for Low Power

Support for 1.5-V-Only Systems

Low-Impedance Flash Switches

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

ProASIC3 Product Family

A3P030

QN132

VQ100

30 k

768

1 k

–

A3P060

VQ100

TQ144

FG144

1,536

60 k

1 k

Yes

A3P125

VQ100

TQ144

PQ208

FG144

125 k

3,072

133

Yes

1 k

ProASIC3E Flash FPGAs

Advanced I/O

Clock Conditioning Circuit (CCC) and PLL

(except A3P030)

SRAMs and FIFOs (except A3P030)

FG144, FG256

•

A3P250

VQ100

PQ208

250 k

6,144

Enhanced High-Speed, Very Long-Line Network

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages – Up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except

A3P030), and LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL and LVDS (A3P250

and above)

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable I/Os (A3P030 only)

Programmable Output Slew Rate and Drive Strength

Weak Pull-Up/Down

IEEE1149.1 (JTAG) Boundary-Scan Test

Pin-Compatible Packages Across the ProASIC3 Family

Six CCC Blocks Total, One with an Integrated PLL

Flexible

Capabilities

Wide Input Frequency Range (1.5 MHz to 350 MHz)

Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,

x9, x18 Organizations Available)

True Dual-Port SRAM (except x18)

24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

Programmable Embedded FIFO Control Logic

157

Yes

1 k

Phase

FG144, FG256,

datasheet.

See Actel’s website for the latest version of the datasheet.

A3P400

PQ208

FG484

400 k

9,216

194

Yes

1 k

Shift,

Multiply/Divide,

FG144, FG256,

A3P600

13,824

PQ208

FG484

600 k

108

227

Yes

1 k

Advanced v0.2

FG256, FG484

A3P1000

and

FG144,

24,576

PQ208

1 M

144

288

Yes

1 k

™

Delay

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