MC74ACT153DG ON Semiconductor, MC74ACT153DG Datasheet - Page 3
![IC MUX DUAL 4INPUT HS 16-SOIC](/photos/5/67/56711/488-16-soic_sml.jpg)
MC74ACT153DG
Manufacturer Part Number
MC74ACT153DG
Description
IC MUX DUAL 4INPUT HS 16-SOIC
Manufacturer
ON Semiconductor
Series
74ACTr
Type
Multiplexerr
Datasheet
1.MC74ACT153DR2G.pdf
(12 pages)
Specifications of MC74ACT153DG
Circuit
2 x 4:1
Independent Circuits
1
Current - Output High, Low
24mA, 24mA
Voltage Supply Source
Single Supply
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Logical Function
Mux
Configuration
2 x 4:1
Number Of Inputs
8
Number Of Outputs
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
SOIC
Dc
0635
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
S
E
S
0
a
1
I
E
0a
a
Figure 2. Logic Symbol
I
0a
I
1a
I
Z
2a
I
a
1a
NOTE:
I
3a
Z
a
I
0b
I
Z
1b
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
b
I
2a
I
2b
I
3b
E
b
I
3a
Figure 3. Logic Diagram
http://onsemi.com
S
1
3
multiplexer. It can select two bits of data from up to four
sources under the control of the common Select inputs (S
S
active−LOW Enables (E
the outputs independently. When the Enables (E
HIGH, the corresponding outputs (Z
The MC74AC153/74ACT153 is the logic implementation
of a 2−pole, 4−position switch, where the position of the
switch is determined by the logic levels supplied to the two
Select inputs. The logic equations for the outputs are shown
below.
S
1
0
The MC74AC153/74ACT153 is a dual 4−input
Z
Z
). The two 4−input multiplexer circuits have individual
a
b
= E
= E
a
b
I
0b
•
•
(I
(I
0a
FUNCTIONAL DESCRIPTION
0b
•
•
S
S
1
1
•
•
S
S
0
0
I
+I
1b
+I
1a
1b
a
•
•
,E
S
S
1
Z
1
b
•
b
•
S
) which can be used to strobe
S
0
0
I
+I
2b
+I
2a
2b
•
•
a
S
S
, Z
1
1
•
•
S
b
S
) are forced LOW.
0
0
+I
I
3b
+I
3a
E
3b
b
•
•
S
S
1
1
•
a
•
S
, E
S
0
0
)
)
b
) are
0
,