HI-3282PJI HOLTIC [Holt Integrated Circuits], HI-3282PJI Datasheet
HI-3282PJI
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HI-3282PJI Summary of contents
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... GENERAL DESCRIPTION The HI-3282 is a silicon gate CMOS device for interfacing the ARINC 429 serial data bus to a 16-bit parallel data bus. Two receivers and an independent transmitter are provided. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol ...
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... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. "ONES" data output from transmitter. ...
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... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3282 contains 11 data flip flops whose D inputs are con- nected to the data bus and clocks connected to flip flop provides options to the user as follows: DATA BUS FUNCTION CONTROL PIN BD04 PAREN Enables parity bit insertion into ...
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... The data flag for a receiver will remain low until after both ARINC bytes from that receiver are retrieved. This is LOW SPEED accomplished by activating to retrieve the first byte and activating retrieve the second byte. 10 ± ...
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... Control register bit BD04 (PAREN) enables parity bit insertion into transmitter data bit 32. Parity is always inserted if DBCEN is open or high. If DBCEN is low, logic 0 on PAREN inserts data on bit 32, and logic 1 on PAREN inserts parity on bit 32. The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd ...
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... SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read also being loaded into the FIFO and the transmitter FIFO is always the same loaded with the lower byte of the data word first ...
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... PL2EN TX/R ENTX t ENDAT 429DO or 429DO 429DI BIT 32 D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX 429DO HI-3282 BYTE 1 VALID t DWSET t DWHLD PL12 ARINC BIT DATA DATA BIT 1 BIT 2 t END ENEN EN t ENSEL t SELEN t PLEN ...
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... Input Source I IL Differential GND Vcc C H Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source I IL DCBEN Pin Output Sink ...
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... Setup - DATA BUS Valid to Hold - Delay - TRANSMISSION TIMING Spacing - Delay - ENTX HIGH to 429DO or Delay - ENTX HIGH to 429DO or Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing HI-3282 ...
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... ADDITIONAL HI-3282 PIN CONFIGURATIONS PIN CONFIGURATION HI-3282 (See page 1 for the 44-pin Plastic QFP) (Top View) HOLT INTEGRATED CIRCUITS 10 ...
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... PART PACKAGE NUMBER DESCRIPTION 44 PIN PLASTIC QUAD FLATPACK (PQFP) HI-3282PQI 44 PIN PLASTIC QUAD FLATPACK (PQFP) HI-3282PQT 44 PIN PLASTIC J-LEAD PLCC HI-3282PJI 44 PIN PLASTIC J-LEAD PLCC HI-3282PJT 40 PIN CERAMIC SIDE-BRAZED DIP HI-3282CDI 40 PIN CERAMIC SIDE-BRAZED DIP HI-3282CDT 40 PIN CERAMIC SIDE-BRAZED DIP HI-3282CDM ...
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... PLASTIC PLCC PIN NO. 1 .045 x 45° .690 .005 (17.526 .127) SQ. .172 .008 (4.369 .203) (15.494 .508) HI-3282 PACKAGE DIMENSIONS 2.020 MAX (51.308 MAX) .050 TYP (1.270 TYP) .085 .009 (2.159 .018 TYP .100 BSC (.457 TYP) (2.540 BSC) PIN NO. 1 IDENT .045 x 45° ...
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... PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A .097 MAX. (2.45) HI-3282 PACKAGE DIMENSIONS .394 ± .004 (10.0 ± .10) SQ. .079 +.004 / -.006 (2.00 +.10 / -.15) .008 (.20 R) HOLT INTEGRATED CIRCUITS 13 inches (millimeters) Package Type: 44PQS .007 MAX. (.17) .0315 BSC (.80 BSC) .014 ± ...