HI-3587PCI HOLTIC [Holt Integrated Circuits], HI-3587PCI Datasheet
HI-3587PCI
Related parts for HI-3587PCI
HI-3587PCI Summary of contents
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... directly N N Pin Plastic Quad Flat Pack (PQFP) HOLT INTEGRATED CIRCUITS www.holtic.com HI-3587 ARINC 429 (Top View BOUT27 32 - BOUT37 HI-3587PCI TFLAG HI-3587PCT Pin Plastic 7mm x 7mm Chip-Scale Package (QFN BOUT27 32 - BOUT37 HI-3587PQI ...
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... SPI interface serial data input CS INPUT Chip select. Data is shifted into SI and out of SO when SCK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK GND POWER Chip 0V supply ACLK INPUT Master timing source for the ARINC 429 transmitter ...
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... Transmission enabled by this instruction only if Control Register bit 13 is zero 12 None Note 1: This instruction is reserved for factory test only. If executed 1,024 data bits may be output from the SO pin. HI-3587 Table 1 lists all instructions. Instructions that perform a reset or set, or enable transmission are executed after the last SI bit is ...
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... HI-3587 STATUS REGISTER The HI-3587 contains an 8-bit Status Register which can be interrogated to determine status of the ARINC Transmit FIFO. The Status Register is read using SPI instruction 0A hex. Unused bits are undefined and may be read as either “1” or “0”. The following table defines the Status Register bits ...
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... Once the Transmit FIFO is empty and transmission of the last word is complete, the FIFO can be loaded with new data which is held until the next SPI 12 hex instruction is executed. Once transmission is enabled, the FIFO positions are incremented with the top register loading into the data transmission shift register ...
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... ARINC outputs. Loading CR10 to 40 Clocks “1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is 40 Clocks set by an on-chip resistor and capacitor and tested to be within 320 Clocks ARINC 429 requirements. LINE DRIVER OUTPUT PINS The HI-3587 AOUT37 and BOUT37 pins have 37 ...
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... DIFF (AOUT - BOUT) 10% one level HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3587PCI and HI-3587PCT use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die. To enhance thermal dissipation, the HI-3587 ...
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... Momentary current OUT Output Sink OUT Output Source OUT C O VDD DD1 I DD2 I EE1 HOLT INTEGRATED CIRCUITS 8 (Hi-Temp): .....-55°C to +125°C LIMITS MIN TYP 80% VDD 20% VDD -1.5 250 -600 4.50 5.00 -0.25 9.0 10.0 -0 -100 A µ 90%VDD = 1.0mA 10% VDD = 0. 3.15 4.75 -4.75 2 ° ...
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... SO high-impedance after SCK falling edge TRANSMITTER TIMING SPI transmit data write or FIFO clear instruction to TFLAG (Empty or Full) SPI instruction to ARINC 429 data output - Hi Speed SPI instruction to ARINC 429 data output - Lo Speed Delay TFLAG high after enable transmit - Hi Speed Delay TFLAG high after enable transmit - Lo Speed ...
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... DS3587, Rev. NEW 05/08/08 Initial Release Rev. A 06/09/08 Clarified the FIFO description Rev. B 10/10/08 Revised AC Electrical Characteristics Rev. C 05/22/09 Clarified the relationship between SPI bit order and the ARINC 429 bit order Rev. D 06/09/09 Clarified the written description of CR1 and its relationship with ACLK. HI-3587 HOLT INTEGRATED CIRCUITS 10 ...
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... PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A ...