HI-3593PCI HOLTIC [Holt Integrated Circuits], HI-3593PCI Datasheet
HI-3593PCI
Related parts for HI-3593PCI
HI-3593PCI Summary of contents
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... RIN1B - 4 RIN1B- RIN2A- RIN2A - 7 RIN2B - 8 RIN2B- ACLK - 11 HOLT INTEGRATED CIRCUITS www.holtic.com HI-3593 (Top View AMPA 32 - TXAOUT RIN1A- RIN1A - AMPB HI-3593PCI RIN1B - TXBOUT 29 - RIN1B- HI-3593PCT RIN2A- TFULL 27 - TEMPTY RIN2A - 7 HI-3593PCM RIN2B - R1FLAG RIN2B- R1INT 24 - R2FLAG ...
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... Receiver 2 Receiver 1 Receive Status RIN2A RIN2B RIN2B-40 ARINC 429 RIN2A-40 Line Receiver 40 KW RIN1A 40 KW RIN1B RIN1B-40 RIN1A-40 HI-3593 VDD (3.3V) Transmitter ARINC 429 Transmit Data FIFO Transmit Status Transmit Control 3.3V Label Receive Control Filter Bit Map Memory ARINC 429 ARINC 429 ...
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... CS INPUT Chip Select. Data is shifted into SI and out of SO when SI INPUT SPI interface serial data input SCLK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK SO OUTPUT SPI interface serial data output GND POWER Chip 0V supply MB1-1 OUTPUT ...
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... Read Receiver 2 Priority-Label Register #2, ARINC429 bytes 2,3 & 4 (bits 9 - 32) 0xCC R 3 Read Receiver 2 Priority-Label Register #3, ARINC429 bytes 2,3 & 4 (bits 9 - 32) 0xD0 R 1 Read Flag / Interrupt Assignment Register 0xD4 R 1 Read ACLK Division Register 0xFF R 0 Instruction not implemented. No operation. HI-3593 TABLE 1. DEFINED INSTRUCTIONS DESCRIPTION HOLT INTEGRATED CIRCUITS 4 ...
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... If this bit is set, bits 9 and 10 of the received ARINC 429 message must match SD9 and SD10 Received word parity checking is enabled when this bit is set. If “0”, all 32 bits of the received ARINC 429 word are stored without parity checking. When “ ...
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... R 0 This bit is set when the Transmit FIFO contains 32 ARINC 429 messages 1 TFHALF R 0 This bit is set when the Transmit FIFO contains at least 16 ARINC 429 messages 0 TFEMPTY R 1 This bit is set when the Transmit FIFO is empty ACLK DIVISION REGISTER (Write, SPI Op-code 0x38) ...
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... Receiver 1 FIFO or any of the Receiver 1 Priority- Label mail boxes 01 R1INT pulses high when a message is received in Receiver 1 Priority-Label mail box #1 10 R1INT pulses high when a message is received in Receiver 1 Priority-Label mail box #2 11 R1INT pulses high when a message is received in Receiver 1 Priority-Label mail box #3 00 ...
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... The first eight bits that appear on the ARINC 429 bus are the label byte. The next twenty three bits comprise a data field which presents data in a variety of formats defined in the ARINC 429 specification. The last bit transmitted is an odd parity bit. ...
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... When the receive signal is out- “ side the differential voltage range defined for any shift regis- “ ter, a “0” is clocked. Only one shift register can clock a “1” for 28 MHz any given sample. All three registers clock zeros if the differ- 30 MHz ential input voltage is between defined state voltage bands ...
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... Because the ARINC 429 label byte value is pre-programmed for each register it is not necessary to store it when words are received. This allows a shorter and faster access of the data field using SPI Op-Codes 0xA4, 0xA8 and 0xAC (Receiver 1 Priority-Label Registers #1, #2 and #3) or 0xC4, 0xC8 and 0xCC (Receiver 2 Priority-Label Registers #1, #2 and #3) ...
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... R1FLAG (Receiver 1) and R2FLAG (Receiver 2) pins. Flag / Interrupt Assignment Register bits and 0 select which flag appears. Additionally, a FIFO not empty option may be programmed for the R1FLAG / R2FLAG pins causing the pin to go high any time at least one word is available in the FIFO. HOLT INTEGRATED CIRCUITS ...
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... Once the Transmit FIFO is empty and transmission of the last word is complete, the FIFO can be loaded with new data which is held until the next SPI 0x40 instruction is executed. Once transmission is enabled, the FIFO positions are incremented with the top register loading into the data transmission shift register ...
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... LINE RECEIVER INPUT PINS The HI-3593 has two sets of Line Receiver input pins for each of the two receivers, RINxA/B and RINxA/B-40. Only one pair may be used to connect to the ARINC 429 bus. The unused pair must be left floating ...
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... HI-3593 The SPI protocol transfers serial data as 8-bit bytes. Once CS chip select is asserted, the next 8 rising edges on SCK latch input data into the master and slave devices, starting with each byte’s most-significant bit. The HI-3593 SPI can be clocked at 10 MHz. ...
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... HOST SERIAL PERIPHERAL INTERFACE, cont. HI-3593 SPI COMMANDS For the HI-3593, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion Since HI-3593 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte ...
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... TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance TXAOUT ARINC BIT TXBOUT DATA NULL BIT 30 ARINC DATA BIT 31 BIT 32 FLAGS (1) R1INT / R2INT t RFLG (1) Receiver status flag outputs: R1FLAG, R2FLAG, MB1-1, MB1-2, MB1-3, MB2-1, MB2-2, MB2-3 ...
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... TIMING DIAGRAMS (cont.) AOUT BOUT V DIFF (AOUT - BOUT) one level CS SPI INSTRUCTION 0x0C SI TEMPTY / TFULL t TFLG AOUT BOUT HI-3593 OUTPUT WAVEFORMS ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% t 10% rx 90% zero level -10V TRANSMITTING DATA ...
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... HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3593PCx uses a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically isolated from the die. To enhance thermal dissipation, the heat sink can be ABSOLUTE MAXIMUM RATINGS Supply Voltages V ...
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... ARINC output current LOGIC OUTPUTS Output Voltage: Logic "1" Output Voltage Logic "0" Output Voltage Output Current: Output Capacitance: OPERATING VOLTAGE RANGE OPERATING SUPPLY CURRENT Transmitting Data in High-Speed Mode. Transmitting Data in High-Speed Mode. HI-3593 CONDITIONS SYMBOL ONE V Common mode voltages IH ...
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... SPI SI Data hold time after SCK rising edge SO high-impedance after SCK falling edge RECEIVER TIMING Delay - Last bit of received ARINC word to Receive Flag change - Hi Speed Delay - Last bit of received ARINC word to Receive Flag change - Lo Speed Received data available to SPI interface. RxFLAG to ...
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... ORDERING INFORMATION HI - 3593 PART NUMBER PART NUMBER PART NUMBER HI-3593 LEAD FINISH Blank Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) F TEMPERATURE RANGE I -40°C TO +85°C T -55°C TO +125°C M -55°C TO +125°C PACKAGE DESCRIPTION PC 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) ...
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... REVISION HISTORY P/N Rev Date Description of Change DS3593 NEW 02/03/08 Initial Release A 08/11/11 Modified AC Electrical Characteristics for 10 MHZ SPI operation. HI-3593 HOLT INTEGRATED CIRCUITS 22 ...
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... PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) .547 ± .010 (13.90 ± .25) SQ. See Detail A ...