K4H510438A-TCA0 SAMSUNG [Samsung semiconductor], K4H510438A-TCA0 Datasheet - Page 15

• Manufacturer Part Number: K4H510438A-TCA0
• Description: 128Mb DDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

128Mb DDR SDRAM
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make
DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined,
therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode
register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in all bank pre-
charge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in
the same cycle as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles
are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in
the idle state. The mode register is divided into various fields depending on functionality. The burst length uses
A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used
for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for
specific codes for various burst lengths, addressing modes and CAS latencies.
* RFU(Reserved for future use)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
should stay "0" during MRS
cycle.
BA
0
1
0
RFU
BA
Extended Funtions(EMRS)
1
(Existing)MRS Cycle
BA
0
0
A
n
A
~ A
11
A
0
1
8
0
RFU
A
10
DLL Reset
A
Yes
No
9
DLL
CAS Latency
A
8
A
0
0
0
0
1
1
1
1
6
TM
Figure 5. Mode Register Set
A
A
7
A
0
1
0
0
1
1
0
0
1
1
7
5
A
CAS Latency
6
- 15 -
A
0
1
0
1
0
1
0
1
Normal
mode
4
Test
A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
Latency
2.5
2
A
4
A
BT
A
0
1
3
3
REV. 1.0 November. 2. 2000
Burst Length
A
0
0
0
0
1
1
1
1
Sequential
A
Burst Type
Interleave
2
Burst Length
2
A
0
0
1
1
0
0
1
1
A
1
1
A
0
1
0
1
0
1
0
1
A
0
0
Sequential
Reserve
Reserve
Reserve
Reserve
Reserve
Address Bus
Mode Register
2
4
8
Latency
Interleave
Reserve
Reserve
Reserve
Reserve
Reserve
2
4
8