K4S511632C SAMSUNG [Samsung semiconductor], K4S511632C Datasheet - Page 3

• Manufacturer Part Number: K4S511632C
• Description: DDP 512Mbit SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4S511632C
8M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
FUNCTIONAL BLOCK DIAGRAM
clock.
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
* Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
GENERAL DESCRIPTION
ORDERING INFORMATION
The K4S511632C is 536,870,912 bits synchronous high data rate
Dynamic RAM organized as 4 x 8,392,608words by 16bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
K4S511632C-KC/L7C
K4S511632C-KC/L75
K4S511632C-KC/L1H
K4S511632C-KC/L1L
Latency & Burst Length
Programming Register
WE
Data Input Register
Column Decoder
2 x 4M x 16
2 x 4M x 16
2 x 4M x 16
2 x 4M x 16
Part No.
DQM
LWCBR
133MHz(CL=2)
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.1 Sept. 2001
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
54pin