K4H560438E-ZC SAMSUNG [Samsung semiconductor], K4H560438E-ZC Datasheet - Page 3

• Manufacturer Part Number: K4H560438E-ZC
• Description: 256Mb E-die DDR SDRAM Specification 60 FBGA with Pb-Free (RoHS compliant)
• Manufacturer: SAMSUNG [Samsung semiconductor]

DDR SDRAM 256Mb E-die (x4, x8) Pb-Free
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA
• RoHS compliant
Operating Frequencies
*CL : CAS Latency
Ordering Information
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
K4H560438E-ZC/LB3
K4H560438E-ZC/LA2
K4H560438E-ZC/LB0
K4H560838E-ZC/LB3
K4H560838E-ZC/LA2
K4H560838E-ZC/LB0
Part No.
Pb-Free
package
[DQ] (x4,x8)
B3(DDR333@CL=2.5)
64M x 4
32M x 8
133MHz
166MHz
2.5-3-3
Org.
Four banks operation
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Max Freq.
A2(DDR266@CL=2)
133MHz
133MHz
2-3-3
Interface
SSTL2
SSTL2
Rev. 1.1 October, 2004
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
60 FBGA
60 FBGA
Package