SSD1815BT ETC1 [List of Unclassifed Manufacturers], SSD1815BT Datasheet - Page 10

• Manufacturer Part Number: SSD1815BT
• Description: LCD Segment / Common Driver with Controller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
ed as data or command. Data is directed to this module based
upon the input of the D/C pin.
RAM (GDDRAM). If it low, the input at D
Command and it will be decoded and be written to the corre-
sponding command register.
MPU Parallel 6800-series Interface
(D
high indicates a read operation from the Graphic Display Data
RAM (GDDRAM) or the status register. R/W(WR) input Low in-
dicates a write operation to Display Data RAM or Internal Com-
mand Registers depending on the status of D/C input. The
E(RD) input serves as data latch signal (clock) when high provid-
ed that CS1 and CS2 are low and high respectively. Refer to Fig-
ure 11 on page 27 for Parallel Interface Timing Diagram of 6800-
series microprocessors.
with that of the MCU, some pipeline processing is internally per-
formed which requires the insertion of a dummy read before the
first actual display data read. This is shown in Figure 3.
SOLOMON
7
-D
This module determines whether the input data is interpret-
If D/C pin is high, data is written to Graphic Display Data
The parallel interface consists of 8 bi-directional data pins
In order to match the operating frequency of the GDDRAM
0
), R/W(WR), D/C, E(RD), CS1 and CS2. R/W(WR) input
R/W(WR)
data bus
E(RD)
write column address
Figure 3 Display Data Read Back Procedure - Insertion of Dummy Read
N
7
-D
0
dummy read
is interpreted as a
data read1
n
MPU Parallel 8080-series interface
(D
serves as data read latch signal (clock) when low provided that
CS1 and CS2 are low and high respectively. Whether it is display
data or status register read is controlled by D/C. R/W(WR) input
serves as data write latch signal(clock) when high provided that
CS1 and CS2 are low and high respectively. Whether it is display
data or command register write is controlled by D/C. Refer to
Figure 12 on page 28 for Parallel Interface Timing Diagram of
8080-series microprocessor.
quired before the first actual display data read.
MPU Serial interface
data SDA (D
shift register on every rising edge of SCK in the order of D
D
the data byte in the shift register is written to the Display Data
RAM or command register at the same clock. Refer to Figure 13
on Page28 for Serial Interface Timing Diagram.
0
7
. D/C is sampled on every eighth clock to determine whether
-D
The parallel interface consists of 8 bi-directional data pins
Similar to 6800-series interface, a dummy read is also re-
The serial interface consists of serial clock SCK (D
0
), E(RD), R/W(WR), D/C, CS1 and CS2. E(RD) input
data read 2
7
), D/C, CS1 and CS2. SDA is shifted into a 8-bit
n + 1
07/2002
Rev1.6
data read 3
n+2
SSD1815B
6
), serial
7
, D
6
11
,...