MT16VDDF12864HG-202 MICRON [Micron Technology], MT16VDDF12864HG-202 Datasheet - Page 23
![no-image](/images/no-image-200.jpg)
MT16VDDF12864HG-202
Manufacturer Part Number
MT16VDDF12864HG-202
Description
SMALL-OUTLINE DDR SDRAM DIMM
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT16VDDF12864HG-202.pdf
(31 pages)
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
41. For -265, -26A, -262 and -335, I
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. IDD2N specifies the DQ, DQS, and DM to be
be 35mA at 100 MHz.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. IDD2Q is
REF later.
DD
3
N
is specified to
23
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
200-PIN DDR SODIMM
512MB, 1GB (x64)
©2003 Micron Technology, Inc.