W332M64V-100BC WEDC [White Electronic Designs Corporation], W332M64V-100BC Datasheet - Page 6

• Manufacturer Part Number: W332M64V-100BC
• Description: 32Mx64 Synchronous DRAM
• Manufacturer: WEDC [White Electronic Designs Corporation]

BURST TYPE
Accesses within a given burst may be pro grammed to be
either se quen tial or interleaved; this is re ferred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is de ter mined by
the burst length, the burst type and the start ing column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the avail abil i ty
of the fi rst piece of output data. The latency can be set to
two or three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. The I/Os will start driving as a result of the clock
edge one cycle ear li er (n + m - 1), and provided that the
rel e vant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is pro grammed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the op er at ing fre quen cies at which each CAS
latency setting can be used.
Reserved states should not be used as unknown op er a tion
or incompatibility with future versions may result.
February 2005
Rev. 0
White Electronic Designs
Command
Command
CLK
CLK
I/O
I/O
READ
READ
T0
T0
FIGURE. 4 – CAS LATENCY
CAS Latency = 2
T1
T1
NOP
NOP
CAS Latency = 3
t
LZ
t
AC
T2
T2
NOP
NOP
6
t
D
LZ
OUT
t
OH
OPERATING MODE
The nor mal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are re served for future use and/or test modes. The
pro grammed burst length applies to both READ and
WRITE bursts.
Test modes and reserved states should not be used
be cause unknown operation or incompatibility with future
versions may result.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
t
AC
SPEED
-100
-125
-133
T3
T3
NOP
White Electronic Designs Corporation • [phone] • www.wedc.com
D
t
OUT
OH
TABLE 2 – CAS LATENCY
T4
LATENCY = 2
≤ 100
≤ 100
≤ 75
CAS
UNDEFINED
DON'T CARE
ALLOWABLE OPERATING
FREQUENCY (MHz)
W332M64V-XBX
LATENCY = 3
≤ 100
≤ 125
≤ 133
CAS