MT9LSDT1672G-10E MICRON [Micron Technology], MT9LSDT1672G-10E Datasheet - Page 14
![no-image](/images/no-image-200.jpg)
MT9LSDT1672G-10E
Manufacturer Part Number
MT9LSDT1672G-10E
Description
SYNCHRONOUS DRAM MODULE
Manufacturer
MICRON [Micron Technology]
Datasheet
1.MT9LSDT1672G-10E.pdf
(18 pages)
NOTE: 1. This parameter is sampled. V
8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
ZM28_3.p65 – Rev. 4/00
10.
11. AC timing and I
24. There will be an added one-clock latency at the system level due to the register requiring an added clock cycle.
26. Auto precharge mode only. The precharge timing budget (
27. Precharge mode only.
28. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified
30.
32. Parameter guaranteed by design.
5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must transit between V
9. Outputs measured at 1.5V with equivalent load:
range (0°C ≤ T
operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the
requirement is exceeded.
between V
t
last valid data element will meet
transition time is longer than 1ns, then the timing is referenced at V
crossover point.
WRITE is executed.
for the clock pin) during access or precharge states (READ, WRITE, including
be used to reduce the data rate.
t
HZ defines the time at which the output achieves the open circuit condition; it is not a reference to V
AC for -133 at CL = 3 with no load is 4.6ns and is guaranteed by design.
Q
IL
and V
A
≤ +70°C) is ensured.
DD
IH
test have V
) in a monotonic manner.
50pF
t
T = 1ns.
DD
IL
= +3.3V; f = 1 MHz.
= 0V and V
t
OH before going High-Z.
IH
= 3V, with timing referenced to 1.5V crossover point. If the input
14
t
RP) begins 7.5ns/7ns after the first clock delay, after the last
REGISTERED SDRAM DIMMs
IL
(MAX) and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR, and PRECHARGE commands). CKE may
IL
(MIN) and no longer at the 1.5V
8, 16 MEG x 72
IH
t
REF refresh
and V
OH
©1999, Micron Technology, Inc.
ADVANCE
or V
IL
(or
OL
. The