HYS64T64020HM QIMONDA [Qimonda AG], HYS64T64020HM Datasheet - Page 26
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HYS64T64020HM
Manufacturer Part Number
HYS64T64020HM
Description
214-Pin Micro-DIMM-DDR2-SDRAM Modules
Manufacturer
QIMONDA [Qimonda AG]
Datasheet
1.HYS64T64020HM.pdf
(44 pages)
3.3.3
This chapter contains the ODT AC electrical characteristic tables.
1) New units, '
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.11, 2006-11
03062006-HT1R-Z2PY
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, '
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 ×
the ODT resistance is fully on. Both are measured from
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
3 ns is assumed,
LOW and by counting the actual input clock edge.
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
t
CK.AVG
CK
' is used for both concepts. Example:
t
' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit '
AOFD
ODT AC Electrical Characteristics
= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
t
AOFD
. Both are measured from
t
XP
t
CK.AVG
t
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
ODT AC Character. and Operating Conditions for DDR2-667
AOFD
t
AOND
+
, which is interpreted differently per speed bin. For DDR2-667/800,if
, which is interpreted differently per speed bin. For DDR2-667/800,
t
EPR.2PER(MIN)
Values
Min.
2
t
t
2.5
t
t
3
8
AC.MIN
AC.MIN
AC.MIN
AC.MIN
26
+ 2 ns
+ 2 ns
.
t
CK.AVG
Max.
2
t
2
2.5
t
2.5
—
—
AC.MAX
AC.MAX
t
CK +
HYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–A
t
' represents the actual
CK +
t
Micro-DIMM DDR2 SDRAM Modules
+ 0.7 ns
AC.MAX
+ 0.6 ns
t
AC.MAX
+ 1 ns
+ 1 ns
t
CK.AVG
Unit
nCK
ns
ns
nCK
ns
ns
nCK
nCK
Internet Data Sheet
TABLE 16
of the input clock
Note
1)
1)2)
1)
1)
1)3)
1)
1)
1)
t
CK.AVG
t
AOND
is
=