M366S3323CT0 SAMSUNG [Samsung semiconductor], M366S3323CT0 Datasheet - Page 4
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M366S3323CT0
Manufacturer Part Number
M366S3323CT0
Description
PC100 Unbuffered DIMM
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.M366S3323CT0.pdf
(7 pages)
SERIAL PRESENCE DETECT
M366S3323CT0-C1H/C1L
• Organization : 32Mx64
• Composition : 16Mx8 *16
• Used component part # : K4S280832C-TC1H/C1L
• # of rows in module : 2 Rows
• # of banks in component : 4 banks
• Feature : 1,375mil height & double sided component
• Refresh : 4K/64ms
• Contents ;
Byte #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuration type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time from clock@CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock@CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
Row
Rows
density
on this assembly
Function Described
banks
RCD
RP
)
)
RAS
on SDRAM device
)
RRD
)
15.625us, support self refresh
precharge all, auto precharge
Non-buffered, non-registered
Burst Read Single bit Write
+/- 10% voltage tolerance,
& redundant addressing
10ns
10ns
20ns
20ns
20ns
50ns
Function Supported
-1H
6ns
6ns
2ns
1ns
2ns
1, 2, 4, 8 & full page
2
-
-
256bytes (2K-bit)
Rows
t
CCD
Non parity
128bytes
4
SDRAM
2
64 bits
LVTTL
0 CLK
0 CLK
None
2 & 3
banks
Rows
12
10
x8
= 1CLK
-
of 128MB
10ns
12ns
20ns
20ns
20ns
50ns
-1L
6ns
7ns
2ns
1ns
2ns
PC100 Unbuffered DIMM
-
-
A0h
A0h
-1H
60h
60h
00h
00h
14h
14h
14h
32h
20h
10h
20h
Rev 0.1 Apr. 2000
Hex value
0Ch
0Ah
0Eh
80h
08h
04h
02h
40h
00h
01h
00h
80h
08h
00h
01h
8Fh
04h
06h
01h
01h
00h
20h
A0h
C0h
60h
70h
00h
00h
14h
14h
14h
32h
20h
10h
20h
-1L
Note
1
1
2
2
2
2