KMM372F804BS SAMSUNG [Samsung semiconductor], KMM372F804BS Datasheet - Page 6

• Manufacturer Part Number: KMM372F804BS
• Description: 8M x 72 DRAM DIMM with ECC using 4Mx16, 4Mx4 4K Refresh, 3.3V
• Manufacturer: SAMSUNG [Samsung semiconductor]

DRAM MODULE
NOTES
1.
2.
3.
4.
5.
6.
7.
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are V
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the
can be met.
If
access time is controlled exclusively by
Assumes tha
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
V
t
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
WCS
CWD
OL
t
RCD
.
,
t
t
RWD
CWD
is greater than the specified
(min),
,
t
t
RCD
CWD
t
RCD
(max) is specified as a reference point only.
,
t
AWD
t
AWD
t
RCD
t
RCD
t
(max).
and
AWD
ih
(max) limit insures that
/V
t
(min) and
t
WCS
il
CPWD
. V
IH
t
(min) and V
WCS
are not restrictive operat-
IH
(min) and V
t
(min) the cycle is an
t
CPWD
RCD
t
CAC
(max) limit, then
t
.
RWD
IL
t
CPWD
(max) are ref-
IL
t
(max) and
t
RWD
RAC
(min).
(max)
OH
(min),
or
10.
11.
12.
13.
14.
15.
16.
17.
18.
8.
9.
Either
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
can be met.
t
access time is controlled by
If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
t
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
t
t
cycle to the first CAS falling edge in the next cycle.
t
modify-write cycle.
t
edge.
t
sition low.
RAD
ASC
ASC
CP
CWD
CWL
CSR
is specified from the last CAS rising edge in the previous
,
is referenced to earlier CAS falling low before RAS tran-
is specified from W falling edge to the earlier CAS rising
6ns.
is referenced to the later CAS falling edge at word read-
t
is greater than the specified
CAH
t
RCH
are referenced to the earlier CAS falling edge.
or
t
RAD
t
RRH
(max) is specified as reference point only. If
must be satisfied for a read cycle.
t
RAD
(max) limit insures that
t
AA
KMM372F804BS
.
t
RAD
(max) limit, then
t
RAC
(max)