R8A66160SP RENESAS [Renesas Technology Corp], R8A66160SP Datasheet - Page 2

• Manufacturer Part Number: R8A66160SP
• Description: 16-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66160DD/SP
PIN CONFIGURATION ( TOP VIEW )
FUNCTIONAL DESCRIPTION
As R8A66160 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for
LED drive while maintaining low power consumption and allowance for high noises.
Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching.
As for clock input, shift clock input CK
latch operations being made when “L” changes to “H”.
Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers
one by one when a pulse is impressed to CK
When the pulse is impressed to CK
register, and they appear in the parallel data outputs from Q
Outputs Q
To extend the number of bits, use the serial data output SQ
of the 16th bit.
When reset input R is changed to “L”, Q
are reset.
If “H” is impressed to output enable input OE, Q
reach the high impedance state. Furthermore, change in OE does not affect shift operation.
FUNCTION TABLE
REJ03F0261-0100 Rev.1.00 Jan.10.2008
page 2 of 7
Shift
Shift
Shift
Latch
Latch
Latch
operation
operation
operation
Note1:↑
Note1:↑
Note1:↑
Operation mode
Operation mode
Operation mode
Output disable
Output disable
Output disable
t
t
t
1
1
1
, t
, t
, t
Reset
Reset
Reset
Q
Q
Q
X
X
X
q
q
q
q
q
q
Z
Z
Z
2
2
2
0
0
0
0
0
0
Shift t
Shift t
Shift t
Latch t
Latch t
Latch t
Latch t
Shift t
Shift t
Shift t
Latch t
Latch t
Latch t
Latch t
：Change from low-level to high-level
：Change from low-level to high-level
：Output state Q before CK
：Output state Q before CK
：Irrelevant
：Irrelevant
：Contents of shift register before CK
：Contents of shift register before CK
：Contents of shift register
：Contents of shift register
：t
：t
：High Impedance
：High Impedance
A
2
2
~ Q
is set after t
is set after t
1
1
1
1
1
1
PARALLEL DATA
OUTPUTS
SERIAL DATA INPUT
ENABLE INPUT
LATCH CLOCK INPUT
DIRECT RESET INPUT
SHIFT CLOCK INPUT
SERIAL DATA OUTPUT
PARALLEL DATA
OUTPUTS
2
2
2
2
2
2
2
2
P
are open drain outputs.
R
R
R R
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
CK
CK
CK
↑
↑
↑
↑
↑
↑
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
S
S
S
is set
is set
Input
Input
Input
CK
CK
CK
↑
↑
↑
↑
↑
↑
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
(Note: 1)
A
A
A
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
changed
changed
OE
OE
OE
OE
X
X
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
, the contents of the shifting register at that time are stored in a latching
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
S
Z
Z
Z
H
H
H
H
Z
Z
Z
Z
Z
Z
Z
S
S
A
A
A
A
A
A
A
A
A
A
0
0
0
0
0
0
and latch clock input CK
A
changed
changed
Q
Q
V
A
OE
CK
R
CK
GND
SQ
Q
Q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
Q
~ Q
Z
Z
Z
Z
Z
Z
A 0
A 0
A 0
A 0
A 0
A 0
A 0
A 0
A 0
A 0
B
B
B
B
B
B
CC
B
B
B
B
A
B
O
P
0
0
0
0
0
0
S
L
S
P
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
Q
. When A is “L”, the signal of “L” shifts.
P
Z
Z
Z
Z
Z
Z
B 0
B 0
B 0
B 0
B 0
B 0
B 0
B 0
B 0
B 0
C
C
C
C
C
C
C
C
C
C
0
0
0
0
0
0
and SQ
A
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
q
q
q
q
q
~ Q
Z
Z
Z
Z
Z
Z
C 0
C 0
C 0
C 0
C 0
C 0
C 0
C 0
C 0
C 0
10
11
12
D
D
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
P
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
D 0
E
E
E
E
E
E
E
E
E
E
P
0
0
0
0
0
0
reaches the high impedance state, but SQ
QA
QB
A
OE
CKL
R
CKS
SQP
QO
QP
are reset. In this case, shifting and latching register
Q
Q
Q
Q
Q
Q
q
q
q
q
q
q
q
q
q
q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
E 0
E 0
E 0
E 0
E 0
E 0
E 0
E 0
E 0
E 0
F
F
F
F
F
F
F
F
F
F
A
0
0
0
0
0
0
P
Parallel data output
Parallel data output
Parallel data output
~ Q
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
which shows the output of the shifting register
Z
Z
Z
Z
Z
Z
F 0
F 0
F 0
F 0
F 0
F 0
F 0
F 0
F 0
F 0
G
G
G
G
G
G
G
G
G
G
QC
QD
QE
QF
QG
QH
QI
QJ
QK
QL
QM
QN
0
0
0
0
0
0
L
.
P
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
Q
are independent from each other, shift and
.
Z
Z
Z
Z
Z
Z
G 0
G 0
G 0
G 0
G 0
G 0
G 0
G 0
G 0
G 0
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
24
23
22
21
20
19
18
17
16
15
14
13
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
H 0
H 0
H 0
H 0
H 0
H 0
H 0
H 0
H 0
H 0
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
I 0
I 0
I 0
I 0
I 0
I 0
I 0
I 0
I 0
I 0
J
J
J
J
J
J
J
J
J
J
0
0
0
0
0
0
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
q
q
q
q
q
C
D
E
F
G
H
I
J
K
L
M
N
Z
Z
Z
Z
Z
Z
J 0
J 0
J 0
J 0
J 0
J 0
J 0
J 0
J 0
J 0
K
K
K
K
K
K
K
K
K
K
0
0
0
0
0
0
Q
Q
Q
Q
Q
Q
q
q
q
q
q
q
q
q
q
q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
K 0
K 0
K 0
K 0
K 0
K 0
K 0
K 0
K 0
K 0
L
L
L
L
L
L
L
L
L
L
0
0
0
0
0
0
PARALLEL DATA
OUTPUTS
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Z
Z
Z
Z
Z
Z
L 0
L 0
L 0
L 0
L 0
L 0
L 0
L 0
L 0
L 0
M
M
M
M
M
M
M
M
M
M
0
0
0
0
0
0
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
Z
Z
Z
Z
Z
Z
M 0
M 0
M 0
M 0
M 0
M 0
M 0
M 0
M 0
M 0
N
N
N
N
N
N
N
N
N
N
0
0
0
0
0
0
Q
Q
Q
Q
q
q
q
q
q
q
q
q
q
q
Q
Q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
N 0
N 0
N 0
N 0
N 0
N 0
N 0
N 0
N 0
N 0
O
O
O
O
O
O
O
O
O
O
0
0
0
0
0
0
Q
Q
Q
q
q
q
q
q
Q
Q
Q
q
q
q
q
q
P
Q
Q
Q
Q
Z
Z
Z
Z q
Z q
Z q
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
P
P
P
P
P
P
P
P
P
P
0
0
0
0
0
0
does not
output
output
output
Serial
Serial
Serial
SQ
SQ
SQ
data
data
data
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
q
L
L
L
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
P
P
P
P
P
P
P
Remarks
Remarks
Remarks
lighting
lighting
lighting
Output
Output
Output
lights-out
lights-out
lights-out
Output
Output
Output
“H”
“H”
“H”
“L”
“L”
“L”