KMM372V803BK SAMSUNG [Samsung semiconductor], KMM372V803BK Datasheet - Page 5

• Manufacturer Part Number: KMM372V803BK
• Description: 8M x 72 DRAM DIMM with ECC using 8Mx8, 4K 8K Refresh, 3.3V
• Manufacturer: SAMSUNG [Samsung semiconductor]

DRAM MODULE
AC CHARACTERISTICS
NOTES
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Fast page mode cycle time
Fast page mode read-modify-write cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
PDE to Valid PD bit
PDE to PD bit Inactive
1.
2.
3.
4.
5.
6.
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are V
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the
can be met.
If
access time is controlled exclusively by
Assumes tha
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
V
OL
t
RCD
.
Present Detect Read Cycle
is greater than the specified
t
RCD
Parameter
t
RCD
(max) is specified as a reference point only.
t
RCD
t
RCD
(max).
ih
(max) limit insures that
/V
(0 C T
il
. V
IH
(min) and V
IH
A
(min) and V
70 C, V
t
RCD
t
CAC
(max) limit, then
.
IL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(max) are ref-
CC
CSR
CHR
RPC
CPA
PC
PRWC
CP
RASP
RHCP
WRP
WRH
OEA
OED
OEZ
OEH
PD
PDOFF
Symbol
IL
=3.3V 0.3V. See notes 1,2.)
(max) and
t
RAC
(max)
OH
or
Min
10
35
76
10
50
35
15
18
13
10.
11.
8
3
8
5
2
7.
8.
9.
t
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
can be met.
t
access time is controlled by
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
WCS
CWD
RAD
-5
,
is greater than the specified
200K
t
t
Max
t
CWD
RWD
RCH
35
18
18
10
7
(min),
,
or
t
t
CWD
RAD
t
RRH
(max) is specified as reference point only. If
,
t
KMM372V80(8)3BK/BS
AWD
t
Min
AWD
10
40
85
10
60
40
15
20
15
must be satisfied for a read cycle.
8
3
8
5
2
t
RAD
t
and
AWD
-6
(max) limit insures that
t
t
(min) and
WCS
t
AA
CPWD
200K
Max
.
40
20
20
10
7
t
WCS
are not restrictive operat-
t
t
(min) the cycle is an
CPWD
RAD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(max) limit, then
t
RWD
t
CPWD
t
t
RWD
RAC
(min).
Note
3,11
11
11
11
11
11
11
11
11
11
(min),
(max)