EDD5116AFTA5BE Elpida Memory, Inc., EDD5116AFTA5BE Datasheet
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EDD5116AFTA5BE
Manufacturer Part Number
EDD5116AFTA5BE
Description
TSOP
Manufacturer
Elpida Memory, Inc.
Datasheet
1.EDD5116AFTA5BE.pdf
(48 pages)
Specifications of EDD5116AFTA5BE
Date_code
07+
Description
The EDD5108AFTA and the EDD5116AFTA are 512M
bits Double Data Rate (DDR) SDRAM organized as
16,777,216 words
words
write operations are performed at the cross points of
the CK and the /CK. This high-speed data transfer is
realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. They are
packaged in standard 66-pin plastic TSOP (II).
Features
Document No. E0741E20 (Ver. 2.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Power supply: VDD ,VDDQ = 2.6V
Data rate: 400Mbps (max.)
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
4 internal banks for concurrent operation
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Auto precharge option for each burst access
SSTL_2 compatible I/O
Programmable burst length (BL): 2, 4, 8
Programmable /CAS latency (CL): 3
Programmable output driver strength: normal/weak
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
TSOP (II) package with lead free solder (Sn-Bi)
7.8 s maximum average periodic refresh interval
Auto refresh
Self refresh
RoHS compliant
16 bits
EDD5116AFTA-5 (32M words 16 bits, DDR400)
EDD5108AFTA-5 (64M words 8 bits, DDR400)
4 banks, respectively. Read and
8 bits
512M bits DDR SDRAM
4 banks and 8,388,608
0.1V
DATA SHEET
Pin Configurations
/xxx indicates active low signal.
A10(AP)
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
/CAS
/RAS
VDD
DQ0
DQ1
DQ2
DQ3
VDD
VDD
/WE
BA0
BA1
/CS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
A1
A2
A3
A10(AP)
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
LDQS
/CAS
/RAS
VDD
VDD
LDM
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/WE
BA0
BA1
/CS
NC
NC
NC
NC
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66-pin Plastic TSOP(II)
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
(Top view)
X 16
X 8
Elpida Memory, Inc. 2005
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS