LE58QL021JC Legerity, Inc., LE58QL021JC Datasheet
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LE58QL021JC
Manufacturer Part Number
LE58QL021JC
Description
Manufacturer
Legerity, Inc.
Datasheet
1.LE58QL021VC.pdf
(65 pages)
Specifications of LE58QL021JC
Date_code
0502
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LE58QL021JC
Manufacturer:
LEGERITY
Quantity:
20 000
APPLICATIONS
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FEATURES
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ORDERING INFORMATION
Le58QL02JC
Le58QL021JC
Le58QL021VC
Le58QL031JC
Codec function on telephone switch line cards
Low-power, 3.3 V CMOS technology with 5 V tolerant
digital inputs
Software and coefficient compatible to the Le79Q02/
021/031 QSLAC™ device
Performs the functions of four codec/filters
Software programmable:
— SLIC device input impedance
— Transhybrid balance
— Transmit and receive gains
— Equalization (frequency response)
— Digital I/O pins
— Programmable debouncing on one input
— Time slot assigner
— Programmable clock slot and PCM transmit clock edge
Standard microprocessor interface
A-law, µ-law, or linear coding
Single or Dual PCM ports available
— Up to 128 channels (PCLK at 8.192 MHz) per PCM port
— Optional supervision on the PCM highway
1.536, 1.544, 2.048, 3.072, 3.088, 4.096, 6.144, 6.176, or
8.192 MHz master clock derived from MCLK or PCLK
Built-in test modes with loopback, tone generation,
and µP access to PCM data
Mixed state (analog and digital) impedance scaling
Performance guaranteed over a 12 dB gain range
Real Time Data register with interrupt (open drain or
TTL output)
Supports multiplexed SLIC device outputs
Broadcast state
256 kHz or 293 kHz chopper clock for Legerity SLIC
devices with switching regulator
Maximum channel bandwidth for V.90 modems
options
Device
Quad Low Voltage Subscriber Line Audio-Processing Circuit
44-pin PLCC
44-pin PLCC
44-pin TQFP
32-pin PLCC
Le58QL02/021/031 QLSLAC Data Sheet
Package
DESCRIPTION
The Le58QL02/021/031 Quad Low Voltage Subscriber Line
Audio-Processing Circuit (QLSLAC™) devices integrate the
key functions of analog line cards into high-performance, very-
programmable, four-channel codec-filter devices. The
QLSLAC devices are based on the proven design of Legerity’s
reliable SLAC™ device families. The advanced architecture of
the QLSLAC devices implements four independent channels
and employs digital filters to allow software control of
transmission, thus providing a cost-effective solution for the
audio-processing function of programmable line cards. The
QLSLAC devices are software and coefficient compatible to the
QSLAC devices.
Advanced submicron CMOS technology makes the Le58QL02/
021/031 QLSLAC devices economical, with both the
functionality and the low power consumption needed in line
card designs to maximize line card density at minimum cost.
When used with four Legerity SLIC devices, a QLSLAC device
provides a complete software-configurable solution to the
BORSCHT functions.
BLOCK DIAGRAM
RELATED LITERATURE
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080754 Le58QL061/063 QLSLAC™ Device Data Sheet
080761 QSLAC™ to QLSLAC™ Device Design
Conversion Guide
080758 QSLAC™ to QLSLAC™ Guide to New Designs
CHCLK
Analog
VOUT
VOUT
VOUT
VOUT
SLIC
VREF
CD1
CD2
CD1
CD2
CD1
CD2
CD1
CD2
VIN
VIN
VIN
VIN
C3
C4
C5
C3
C4
C5
C3
C4
C5
C3
C4
C5
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
1
1
2
2
3
3
4
4
Le58QL02/021/031
Signal Processing
Signal Processing
Signal Processing
Signal Processing
Channel 1 (CH 1)
Channel 2 (CH 2)
Channel 3 (CH 3)
Channel 4 (CH 4)
Interface
SLIC
(SLI)
Document ID# 080753
Rev:
Distribution:
Le58000 SLAC™Family
Reference
Circuits
Clock
&
INT
C
Public Document
Microprocessor Interface
Time Slot Assigner
Microprocessor
CS
(MPI)
(TSA)
DIO
Date:
Version: 1
QLSLAC™
DCLK
Oct 23, 2002
Dual/Single
Highway
DXA
DRA
TSCA
DXB
DRB
TSCB
FS
PCLK
RST
MCLK/E1
PCM