PL102-10SC PhaseLink Corp., PL102-10SC Datasheet

PL102-10SC

Manufacturer Part Number

PL102-10SC

Description

Manufacturer

PhaseLink Corp.

Datasheet

1.PL102-10SC.pdf (7 pages)

Specifications of PL102-10SC

Case

SOP8

Date_code

08+

Current page: 1 of 7
Download datasheet (169Kb)

FEATURES

 Frequency range:

 Internal phase locked loop will allow spread

 Zero input - output delay

 Less than 700 ps device - device skew

 Less than 200 ps skew between outputs

 Less than 100 ps cycle - cycle jitter

 2.5V or 3.3V power supply operation

 Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS

DESCRIPTION

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed

clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the

input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between

the input and output is less than 350 ps, the device acts as a zero delay buffer.

BLOCK DIAGRAM

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 3/31/08 Page 1

spectrum modulation on reference clock to pass

to outputs.

compliant package

− 15 ~ 170MHz @ 3.3V

− 15 ~ 145MHz @ 2.5V

REFIN

PLL

PIN CONFIGURATION

REFIN

CLK1

CLK2

GND

REFIN

CLK1

Low Skew Output Buffer

GND

CLKOUT

CLK1

CLK2

SOT23-6L

SOP-8L

CLK2

VDD

CLKOUT

DNC

VDD

Related parts for PL102-10SC

Related keywords

PL102-10SC datasheet
PL102-10SC data sheet
PL102-10SC pdf datasheet
PL102-10SC component
PL102-10SC part
PL102-10SC distributor
PL102-10SC RoHS
PL102-10SC datasheet download