VP101 ZARLINK [Zarlink Semiconductor Inc], VP101 Datasheet
VP101
Available stocks
Related parts for VP101
VP101 Summary of contents
Page 1
THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS ...
Page 2
... The device uses video control inputs (BLANK, SYNC and REF WHITE) to provide the VP101 with the video pedestal levels required to generate RS-343A compatible video signals into a doubly-terminated 75 alternatively to produce RS-170 video signals across a singly-terminated 75 load ...
Page 3
... VP101 RECOMENDED OPERATING CONDITIONS Parameter Supply voltage Ambient operating temperature Output load Reference voltage (internal or external) FS ADJUST resistor THERMAL CHARACTERISTICS Thermal resistance, chip-to-case Thermal resistance, chip-to-ambient 2 Fig.2 functional block diagram of VP101 Symb Value ol Min. Typ. Max. V 4.75 5.00 5. +70 amb R 37 ...
Page 4
... LSB 8.96 mA 111 LSB LSB +1 1. ppm/ C VP101-3 Units Min. Typ. Max. 30 MHz 33 100 pV-sec Clock 100 140 mA VP101 Conditions binary coding RS-343A tolerances assumed Conditions max AA 3 ...
Page 5
... VP101 CIRCUIT DESCRIPTION As shown in the Fig. 2, the VP101 contains three 8-bit D-A converters, input latches, and a loop amplifier. On the rising edge of each clock cycle, (see Fig. 4), 24 bits of colour information ( latched into the device and presented to the three 8-bit D-A converters ...
Page 6
... G -G and B -B SYNC, BLANK, and REFWHITE (V) 111 LSBs ( ) resistor is equal to 32 LSBs. note that the IRE SET is connected to IOG) is: SYNC (V) 387 LSBs ( ) is defined as: SET (V) REF 276 LSBs SET . AA VP101 - SYNC and the SYNC AA 5 ...
Page 7
... SET Similarly for generation of RS-170-compatible video recommended that a singly terminated 75 with an R value of about 774 . If the VP101 is not driving SET a large capacitive load, there will be negligible difference in video quality between doubly terminated 75 terminated 75 loads.t If driving a large capacitive load (load RC >1/20 recommended that an output buffer with unloaded gain > ...
Page 8
... Digital Signal Interconnect The digital signal lines to the VP101 should be isolated as much as possible from the analog circuitry. Due to the high clock rates used, the clock lines to the VP101 should be as short as possible to minimise noise pickup. Any pull-up resistors used on the inputs should be connected to the regular PCB power plane, not to the analog power plane ...
Page 9
... VP101 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...
Page 10
For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...