COREAHB ACTEL [Actel Corporation], COREAHB Datasheet

no-image

COREAHB

Manufacturer Part Number
COREAHB
Description
CoreAHB
Manufacturer
ACTEL [Actel Corporation]
Datasheet
CoreAHB
Product Summary
Intended Use
Key Features
Benefits
Supported Device Families
Synthesis and Simulation Support
Verification and Compliance
January 2008
© 2008 Actel Corporation
• CoreAHB Provides an AHB Bus Fabric and Is
• Supplied in SysBASIC Core Bundle
• Implements a Multi-Master AMBA AHB Bus Fabric
• Up to 3 AHB Masters Can Be Accommodated
• Up to 16 AHB Slave Devices Are Supported
• Automatic Stitching to AHB Slaves and Masters in
• Supports Swapping (or remapping) of Slave Slots 0
• Allows Easy Inter-Connection of AHB Masters and
• Devices Can Be Automatically Connected to
• Compatible with CoreMP7 and Cortex™-M1
• Fusion
• IGLOO™
• IGLOOe
• ProASIC
• ProASIC3
• ProASIC3E
• Synthesis: Synplicity
• Simulation: ModelSim
• Compliant with AMBA
Intended for Use in an AMBA Subsystem where
Multiple AHB Masters are Present
CoreConsole
and 1 to Facilitate Processor Boot
Slaves in a Subsystem
CoreAHB Using the Auto Stitch Feature in
CoreConsole, which Allows for Rapid System
Development
®
3L
®
v 2 .1
Contents
General Description
CoreAHB implements a multi-master AHB bus fabric. Up
to 3 masters and 16 slaves can be connected to CoreAHB.
A block diagram of CoreAHB is shown in
AHB slave slot is allocated 256 megabytes of memory
space and all slave slots are accessible from each master
connection.
Figure 1 • CoreAHB Block Diagram
Master 1
Master 2
General Description ................................................... 1
Arbitration Scheme .................................................... 2
Remapping ................................................................. 2
Connecting CoreAHB in CoreConsole ....................... 2
CoreAHB Port List ....................................................... 3
Resource Requirements ............................................. 5
Ordering Information ................................................ 5
List of Changes ........................................................... 6
Datasheet Categories ................................................. 6
Master 3
Arbitration
Masters to Slaves
Slaves to Masters
Mulitplexer
Multiplexer
Decoder
Address
Figure
.
. .
Slave 0
Slave 1
Slave 2
Slave 15
1. Each
1

Related parts for COREAHB

COREAHB Summary of contents

Page 1

... List of Changes ........................................................... 6 Datasheet Categories ................................................. 6 General Description CoreAHB implements a multi-master AHB bus fabric masters and 16 slaves can be connected to CoreAHB. A block diagram of CoreAHB is shown in AHB slave slot is allocated 256 megabytes of memory space and all slave slots are accessible from each master connection. ...

Page 2

... Master 1 has the lowest priority and is the default bus master. The main subsystem processor (such as CoreMP7) is normally connected to this master connection. Connecting CoreAHB in CoreConsole Table 1 lists the connections present on CoreAHB and describes how to connect these in CoreConsole. Table 1 • CoreAHB Bus Connections CoreConsole Connection Label HCLK ...

Page 3

... Table 1 • CoreAHB Bus Connections (Continued) CoreConsole Connection Label AHB mirrored master 1 interface AHBmmaster1 AHB mirrored master 2 interface AHBmmaster2 AHB mirrored master 3 interface AHBmmaster3 AHBmslave0 AHBmslave1 AHBmslave2 AHBmslave3 AHBmslave4 AHBmslave5 AHBmslave6 AHBmslave7 AHBmslave8 AHBmslave9 AHBmslave10 AHBmslave11 AHBmslave12 AHBmslave13 AHBmslave14 AHBmslave15 CoreAHB Port List Table 2 on page 4 lists the ports present on the AHB Bus component ...

Page 4

... CoreAHB Table 2 • CoreAHB Port List Signal Direction Description HCLK Input Bus clock. This clock times all bus transfers. All signal timings are related to the rising edge of HCLK. HRESETn Input Reset. The bus reset signal is active low and is used to reset the system and the bus. This is the only active low AHB signal ...

Page 5

... The utilization for CoreAHB in a Fusion, IGLOO, ProASIC3L, or ProASIC3/E device is 1,300 tiles. Ordering Information CoreAHB is included in the SysBASIC core bundle that is supplied with the Actel CoreConsole IP Deployment Platform tool. The obfuscated RTL version of SysBASIC (SysBASIC-OC) is available for free with CoreConsole. The source RTL version of SysBASIC (SysBASIC-RM) can be ordered through your local Actel sales representative ...

Page 6

... Requirements" section Advanced v0.1 The "Product Summary" section Table 1 • CoreAHB Bus Connections HCLK and HRESETn. Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these ...

Page 7

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court River Court, Meadows Business Park Mountain View, CA Station Approach, Blackwater 94043-4655 ...

Related keywords