LH531024 SHARP [Sharp Electrionic Components], LH531024 Datasheet
LH531024
Related parts for LH531024
LH531024 Summary of contents
Page 1
... Single +5 V power supply JEDEC standard EPROM pinout (DIP) Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) DESCRIPTION The LH531024 is a mask-p rogrammable ROM organized as 65,536 16 bits fabricated using silicon-gate CMOS process technology. CMOS 1M (64K PIN CONNECTIONS 40-PIN DIP ...
Page 2
... COLUMN SELECTOR TIMING SENSE AMPLIFIER GENERATOR OUTPUT BUFFER GND Figure 3. LH531024 Block Diagram SIGNAL GND CMOS 1M MROM MEMORY MATRIX (65,536 x 16 ...
Page 3
... NOTE: Pin numbers apply to the 44-pin QFJ. COLUMN SELECTOR TIMING SENSE AMPLIFIER GENERATOR OUTPUT BUFFER GND Figure 4. LH531024 Block Diagram LH531024 MEMORY MATRIX (65,536 x 16 ...
Page 4
... LH531024 TRUTH TABLE – High – NOTE ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply voltage V CC Input voltage V IN Output voltage V OUT Operating temperature Topr Storage temperature Tstg RECOMMENDED OPERATING CONDI- TIONS ( +70 C) ...
Page 5
... MIN. TYP. MAX. UNIT 100 ns 100 ns 100 RATING (NOTE) t ACE (NOTE (NOTE) DATA VALID , t , and t , from address AA ACE OE Figure 5. Timing Diagram LH531024 NOTE 1 t CHZ t OHZ t OH 531024-5 5 ...
Page 6
... LH531024 PACKAGE DIAGRAMS 40DIP (DIP040-P-0600 52.30 [2.059] 51.70 [2.035] 2.54 [0.100] 0.60 [0.024] TYP. 0.40 [0.016] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012 26.50 [1.043] 26.10 [1.028] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 6 21 13.45 [0.530] 12.95 [0.510] 20 0.30 [0.012] ...
Page 7
... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH531024 Device Type Example: LH531024N (CMOS 1M (64K x 16) Mask-Programmable ROM, 40-pin, 525-mil SOP 16.60 [0.654] 17.60 [0.693 44-pin, 650-mil QFJ (PLCC) X Package D 40-pin, 600-mil DIP (DIP040-P-0600) N 40-pin, 525-mil SOP (SOP040-P-0525) ...