LH532048 SHARP [Sharp Electrionic Components], LH532048 Datasheet

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LH532048

Manufacturer Part Number
LH532048
Description
CMOS 2M (128K x 16) MROM
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
LH532048
FEATURES
DESCRIPTION
organized as 131,072
silicon-gate CMOS process technology.
The LH532048 is a 2M-bit mask-programmable ROM
131,072 words
Access time: 100 ns (MAX.)
Static operation
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Power consumption:
Packages:
Operating: 412.5 mW (MAX.)
Standby: 550 W (MAX.)
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
16 bit organization
16 bits. It is fabricated using
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
44-PIN PLCC
GND
D
D
D
NC
D
D
D
D
D
D
12
10
Figure 1. Pin Connections for DIP and
11
7
9
8
6
5
4
Figure 2. Pin Connections for QFJ
10
12
13
14
15
16
17
11
7
8
9
18 19 20 21 22 23 24 25 26 27 28
6
CMOS 2M (128K
GND
5
D
D
D
D
D
NC
OE
CE
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
10
11
9
8
7
6
5
4
3
2
0
1
4
(PLCC) Package
SOP Packages
10
12
13
14
15
16
17
18
19
20
11
3
2
3
4
5
6
7
8
9
1
2
1 44 43 42 41 40
40
39
38
37
36
35
34
33
32
30
29
28
27
26
25
24
23
22
31
21
A
A
A
A
A
A
A
V
NC
A
A
A
A
A
A
A
GND
A
A
A
12
6
4
3
2
1
0
CC
16
15
14
13
11
10
9
8
7
5
16) MROM
TOP VIEW
TOP VIEW
39
38
37
36
35
34
33
32
30
29
31
532048-2
532048-1
A
A
A
A
A
GND
NC
A
A
A
A
13
12
11
10
9
8
7
6
5
1

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LH532048 Summary of contents

Page 1

... Operating: 412.5 mW (MAX.) Standby: 550 W (MAX.) Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 44-pin, 650-mil QFJ (PLCC) DESCRIPTION The LH532048 is a 2M-bit mask-programmable ROM organized as 131,072 16 bits fabricated using silicon-gate CMOS process technology. CMOS 2M (128K PIN CONNECTIONS 40-PIN DIP 40-PIN SOP ...

Page 2

... Address input – D Data output Chip enable input OE Output enable input 2 MEMORY MATRIX (131,072 x 16) COLUMN SELECTOR TIMING SENSE AMPLIFIER GENERATOR Figure 3. LH532048 Block Diagram SIGNAL V CC GND NC CMOS 2M MROM ...

Page 3

... BUFFER BUFFER NOTE: Pin numbers apply to the 44-pin QFJ. MEMORY MATRIX (131,072 x 16) COLUMN SELECTOR TIMING SENSE AMPLIFIER GENERATOR Figure 4. LH532048 Block Diagram LH532048 GND ...

Page 4

... LH532048 TRUTH TABLE CE OE DATA OUTPUT H X High High – NOTE High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply voltage V CC Input voltage V IN Output voltage V OUT Operating temperature Topr Storage temperature Tstg RECOMMENDED OPERATING CONDITIONS (T ...

Page 5

... AA ACE 10 + MIN. MAX. 100 100 100 RATING (NOTE) t ACE (NOTE (NOTE) DATA VALID Figure 5. Timing Diagram LH532048 UNIT NOTE CHZ t OHZ t OH 532048-5 5 ...

Page 6

... LH532048 PACKAGE DIAGRAMS 40DIP (DIP040-P-0600 52.30 [2.059] 51.70 [2.035] 2.54 [0.100] 0.60 [0.024] TYP. 0.40 [0.016] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 40SOP (SOP040-P-0525) 1.27 [0.050] TYP. 0.50 [0.020] 0.30 [0.012 26.50 [1.043] 26.10 [1.028] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 6 21 13.45 [0.530] 12.95 [0.510] 20 0.30 [0.012] ...

Page 7

... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH532048 Device Type Package Example: LH532048D (CMOS 2M (128K x 16) Mask-Programmable ROM, 40-pin, 600-mil DIP 16.60 [0.654] 17.60 [0.693] 17.40 [0.685 44-pin, 650-mil QFJ (PLCC 40-pin, 600-mil DIP (DIP040-P-0600) ...

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