K6R1004C1B SAMSUNG [Samsung semiconductor], K6R1004C1B Datasheet
K6R1004C1B
Related parts for K6R1004C1B
K6R1004C1B Summary of contents
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... K6R1004C1B-C Document Title 256Kx4 Bit (with OE) High Speed Static RAM(5.0V Operating), Revolutionary Pin out. Revision History Rev No. History Rev. 0.0 Initial release with Design Target. Rev.1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Rev.2.0 Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete L-version. ...
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... The K6R1004C1B is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6R1004C1B uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAM- SUNG s advanced CMOS process and designed for high- speed circuit technology ...
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... K6R1004C1B-C ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... OHZ PRELIMINARY Preliminary PRELIMINARY CMOS SRAM Value 3ns 1.5V See below & t OLZ OHZ +5.0V 480 5pF* K6R1004C1B-12 Unit Max Min Max - ...
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... Controlled CS=OE (WE OLZ t LZ(4,5) Valid Data PRELIMINARY Preliminary PRELIMINARY CMOS SRAM K6R1004C1B-12 Unit Min Max Valid Data t HZ(3,4,5) t OHZ ...
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... K6R1004C1B-C NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced ...
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... K6R1004C1B-C TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; ...
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... K6R1004C1B-C PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 8 - PRELIMINARY Preliminary PRELIMINARY CMOS SRAM Units:millimeters/Inches 9.40 0.25 0.370 0.010 +0.10 0.20 -0.05 +0.004 0.008 -0.002 0.69 MIN 0.027 ) 0.10 3.76 MAX MAX 0.004 0.148 ) Rev 2.0 February 1998 ...