K6R1004C1C SAMSUNG [Samsung semiconductor], K6R1004C1C Datasheet
K6R1004C1C
Available stocks
Related parts for K6R1004C1C
K6R1004C1C Summary of contents
Page 1
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P Document Title 256Kx4 Bit (with OE) High-Speed CMOS Static RAM(5.0V Operating). Revision History Rev. No. History Rev. 0.0 Initial release with Preliminary. Rev. 1.0 Release to Final Data Sheet. 1.1. Delete Preliminary. Rev. 2.0 Add 10ns & Low Power Ver. Rev. 3.0 Delete 20ns speed bin The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications ...
Page 2
... The K6R1004C1C is a 1,048,576-bit high-speed Static Ran- dom Access Memory organized as 262,144 words by 4 bits. The K6R1004C1C uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAM- SUNG s advanced CMOS process and designed for high- speed circuit technology ...
Page 3
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
Page 4
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P AC CHARACTERISTICS ( TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads Output Loads(A) D OUT Capacitive Load consists of all components of the test environment. READ CYCLE* Parameter Symbol ...
Page 5
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P WRITE CYCLE* Parameter Symbol Write Cycle Time t WC Chip Select to End of Write t CW Address Set-up Time t AS Address Valid to End of Write t AW Write Pulse Width(OE High Write Pulse Width(OE Low) t WP1 Write Recovery Time t WR Write to Output High-Z ...
Page 6
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
Page 7
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; ...
Page 8
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P DATA RETENTION CHARACTERISTICS* Parameter Symbol V for Data Retention CC Data Retention Current Data Retention Set-Up Time Recovery Time * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-ver only. DATA RETENTION WAVE FORM CS controlled ...
Page 9
... K6R1004C1C-C/C-L, K6R1004C1C-I/C-P PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 #17 #16 21.36 MAX 0.841 20.95 0.12 0.825 0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 9 - PRELIMINARY PRELIMINARY CMOS SRAM Units:millimeters/Inches 9.40 0.25 0.370 0.010 +0.10 0.20 -0.05 +0.004 0.008 -0.002 0.69 MIN 0.027 ) 0.10 3.76 MAX MAX 0.004 0.148 ) Revision 3.0 September 2001 ...