GVT71128D32T-4 ETC1 [List of Unclassifed Manufacturers], GVT71128D32T-4 Datasheet
GVT71128D32T-4
Related parts for GVT71128D32T-4
GVT71128D32T-4 Summary of contents
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... Each memory cell consists of four transistors and two high valued resistors. The GVT71128D32 SRAM integrates 131,072x32 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous ...
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... ADSC# ADV# A1-A0 MODE NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM BYTE 1 WRITE D Q BYTE 2 WRITE D Q BYTE 3 WRITE D Q BYTE 4 WRITE ...
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... BWE# Input- Synchronous 88 GW# Input- Synchronous 89 CLK Input- Synchronous 98 CE# Input- Synchronous 92 CE2# Input- Synchronous November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM PIN ASSIGNMENT (Top View) 100 ...
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... WRITE all bytes H WRITE all bytes L November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM TYPE input- Chip enable: This active HIGH input is used to enable the device. Synchronous Input Output Enable: This active LOW asynchronous input enables the data output drivers. Input- Address Advance: This active LOW input is used to control the internal burst counter ...
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... ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM CE# CE2# CE2 ADSP # ADSC# ADV# ...
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... Thermal Resistance - Junction to Case November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM *Stresses greater than those listed uunder “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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... OE to output in Low output in High-Z Setup Times Address, Controls and Data In Hold Times Address, Controls and Data In CAPACITANCE DERATING DESCRIPTION SYMBOL t Clock to output valid November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM - MIN MAX MIN MAX MIN ...
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... A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE “don’t care” when a byte write enable is sampled LOW. November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM OUTPUT LOADS FOR 3.3V I 3.0V 1.5ns 1.5V 1.5V See Figures 1 and ...
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... BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note) ADV# OE# t KQLZ DQ Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM READ TIMING ...
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... BWE# GW# CE# (See Note) ADV# OE# t KQX DQ Q SINGLE WRITE Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM WRITE TIMING OEHZ D(A1) D(A2) D(A2+1) D(A2+1) BURST WRITE 10 ...
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... BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE# (See Note) ADV# OE# DQ Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active. November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM READ/WRITE TIMING Q(A1) Q(A2) D(A3) Q(A3) Pass Through Single Single Write ...
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... GALVANTECH 100 Pin TQFP Package Dimensions # 1 1.40 + 0.05 1.60 Max Note: All dimensions in Millimeters November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM 16.00 + 0.10 14.00 + 0.10 0.65 Basic 0.30 + 0.08 12 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128D32 0.60 + 0.15 ...
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... GALVANTECH Ordering Information GVT 71128D32 Galvantech Prefix Part Number November 20, 1999 Rev. 11 128K X 32 SYNCHRONOUS BURST SRAM 13 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT71128D32 Temperature (Blank = Commercial I = Industrial) Speed (4 = 4.8ns access/10ns cycle 5 = 5ns access/10ns cycle 6 = 6ns access/12ns cycle ...