K7N161801-FC13 SAMSUNG [Samsung semiconductor], K7N161801-FC13 Datasheet
K7N161801-FC13
Related parts for K7N161801-FC13
K7N161801-FC13 Summary of contents
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K7M163625A K7M161825A Document Title 512Kx36 & 1Mx18-Bit Flow Through NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add JTAG Scan Order 0.2 1. Remove bin -90 2. Updated DC characteristics(ICC,ISB,ISB1,ISB2) 0.3 1. Add x32 org and ...
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... K7M163625A K7M161825A 16Mb NtRAM(Flow Through / Pipelined) Ordering Informa Org. Part Number K7M161825A-QC(I)65/75 1Mx18 K7N161801A-Q(F)C(I)25/20/16/13 K7N161845A-Q(F)C(I)25/20/16/13 K7M163625A-QC(I)65/75 512Kx36 K7N163601A-Q(F)C(I)25/20/16/13 K7N163645A-Q(F)C(I)25/20/16/13 512Kx36 & 1Mx18 Flow-Through NtRAM tion Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2.5 250/200/167/133MHz FlowThrough 3.3 6.5/7.5 ns Pipelined 3.3 250/200/167/133MHz Pipelined 2 ...
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... This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M163625A and K7M161825A are implemented with ...
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K7M163625A K7M161825A PIN CONFIGURATION (TOP VIEW) NC/DQPc 1 DQc 0 2 DQc DDQ 4 V SSQ 5 DQc 2 6 DQc 3 7 DQc 4 8 DQc SSQ 10 V DDQ 11 DQc 6 ...
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K7M163625A K7M161825A PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ N.C. 6 N.C. 7 DQb 8 8 DQb SSQ V 11 DDQ DQb 12 6 DQb 13 5 ...
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... And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time ...
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K7M163625A K7M161825A BEGIN READ READ BURST COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change ...
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K7M163625A K7M161825A TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...
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K7M163625A K7M161825A ASYNCHRONOUS TRUTH TABLE Operation ZZ Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative to V Power Dissipation ...
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K7M163625A K7M161825A DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ) Output Leakage Current Operating Current Standby Current Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High ...
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... To avoid bus contention given vlotage and temperature t The soecs as shown do not imply bus contention because t (0 C,3.465V) than t , which is a Max. parameter(worst case at 70 C,3.135V not possible for two SRAMs on the same board such different voltage and temperatue. 512Kx36 & 1Mx18 Flow-Through NtRAM RL=50 VL=1.5V for 3.3V I for 2 ...
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... When the ZZ pin becomes a logic High, I MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pend- ing operations are completed. similarly, when exiting SLEEP MODE during t while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION ...
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K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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K7M163625A K7M161825A 512Kx36 & 1Mx18 Flow-Through NtRAM - Nov. 2003 Rev 3.0 ...
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K7M163625A K7M161825A PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 512Kx36 & 1Mx18 Flow-Through NtRAM 22.00 0.30 20.00 0.20 (0.58) 0.30 0.10 0.10 MAX 1.40 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 16.00 0.30 ...