A42L8316S-30 AMICC [AMIC Technology], A42L8316S-30 Datasheet - Page 10

• Manufacturer Part Number: A42L8316S-30
• Description: 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
• Manufacturer: AMICC [AMIC Technology]

AC Characteristics (continued)
Test Conditions:
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. t
11. t
12. These parameters are referenced to
13. Access time is determined by the longer of t
14. t
PRELIMINARY
51
52
53
54
#
Input timing reference level: V
Output reference level: V
Output Load: 2TTL gate + CL (50pF)
Assumed t
I
I
An initial pause of 200 s is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8
AC Characteristics assume t
50pF, V
V
between V
Operation within the t
point only. If t
Operation within the t
point only. If t
Assumes three state test load (5pF and a 500 Thevenin equivalent).
Either t
voltage levels.
as electrical characteristics only. If t
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If t
t
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
read-modify-write cycles.
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
CC1
CC1
OFF
WCS
CWD
ASC
IH
Symbol
, I
(min.) and V
, t
and I
t
t
t
(max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
Std
RASS
t
(min.) and t
OEZ
RPS
CHS
CC3
t
WCH
CP
RCH
IL
, I
CC4
T
to achieve t
(min.)
, t
=2ns
CC4
IH
or t
and V
depend on output loading. Specified values are obtained with the outputs open.
RWD
, and I
RCD
RAD
Output Buffer Turn-off Delay from
(
(
RAS precharge time
OE
CAS hold time (
RRH
RAS pulse width
C
(August, 2002, Version 0.1)
C
, t
-B-
AWD
IL
-B-
is greater than the specified t
is greater than the specified t
GND and V
must be satisfied for a read cycle.
IL
(max.) are reference levels for measuring timing of input signals. Transition times are measured
CWD
CC5
.
R
R
PC
self refresh)
self refresh)
RCD
RAD
depend on cycle rate.
t
OH
(min.) and t
AWD
and t
/V
Parameter
(max.) limit insures that t
(max.) limit insures that t
OL
(min.), the cycle is a read-modify-write cycle and the data out will contain data read from
IH
T
IH
C
/V
AWD
=2.0V/0.8V
= 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
(max.)
IL
-B-
(VCC = 3.3V
=2.0V/0.8V
are not restrictive operating parameters. They are included in the data sheet
CPA
R
UCAS
self refresh)
WCS
(max.) values.
VCC.
AA
and
t
RCD
RAD
or t
WCS
0.3V, VSS = 0V, Ta = 0 C to +70 C or -40 C to +85 C)
CAC
LCAS
(max.) limit, then access time is controlled exclusively by t
(max.) limit, then access time is controlled exclusively by t
(min.) and t
Min.
100
RAC
RAC
-50
or t
54
-
CPA
-30
leading edge in early write cycles and to WE leading edge in
(max.) can be met. t
(max.) can be met. t
9
.
Max.
3
-
-
-
WCH
Min.
100
-50
62
-
t
WCH
-35
Max.
(min.), the cycle is an early write cycle
3
-
-
-
RCD
RAD
(max.) is specified as a reference
(max.) is specified as a reference
Min.
100
-50
70
AMIC Technology, Inc.
-
-40
A42L8316 Series
Max.
RWD
3
-
-
-
t
RWD
Unit
ns
ns
ns
s
(min.) , t
AA
CAC
.
Notes
.
8
CWD