A43L2632V-7 AMICC [AMIC Technology], A43L2632V-7 Datasheet - Page 32
A43L2632V-7
Manufacturer Part Number
A43L2632V-7
Description
1M X 32 Bit X 4 Banks Synchronous DRAM
Manufacturer
AMICC [AMIC Technology]
Datasheet
1.A43L2632V-7.pdf
(43 pages)
- Current page: 32 of 43
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PRELIMINARY
Read & Write Cycle with Auto Precharge @Burst Length=4
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
DQM
BS1
BS0
CS
DQ
DQ
WE
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
0
Row Active
(A-Bank)
RAa
RAa
1
(In the case of Burst Length=1 & 2, BRSW mode)
(January, 2005, Version 0.0)
2
3
Row Active
(D-Bank)
RBb
RBb
4
Auto Precharge
Read with
(A-Bank)
CAa
5
6
QAa0
7
QAa0
QAa1
Auto Precharge
(A-Bank/CL=2)
8
Start Point
QAa2
QAa1
9
Auto Precharge
31
(A-Bank/CL=3)
High
Start Point
QAa3
QAa2
10
QAa3
11
12
Auto Precharge
13
Write with
(D-Bank)
DDb0 DDb1 DDb2 DDb3
DDb0
CBb
14
DDb1 DDb2 DDb3
AMIC Technology, Corp.
15
16
17
: Don't care
Auto Precharge
A43L2632
18
Start Point
(D-Bank)
19
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