MAS9191AJ MAS [Micro Analog systems], MAS9191AJ Datasheet - Page 21

• Manufacturer Part Number: MAS9191AJ
• Description: Single Chip AMPS/ETACS/NAMPS Audio/Data Processor
• Manufacturer: MAS [Micro Analog systems]

FUNCTIONS
◆
The device has three 8-bit DACs. The DACs can be
set to the power down mode by using bits
XPDDAC1, XPDDAC2 and XPDDAC3. The DACs
are in power down mode after a reset. The Vref for
the DACs is VDD/2. The output values of the DACs
are entered in 8-bit two’s complement form into
◆
There are two uncommitted inverting operational
amplifiers in the device. The input pins are RXACCIN
and TXACCIN. The output pins are RXACCOUT and
◆
The serial interface has three inputs: SCL (serial
clock), STB (strobe) and SRxD(received data).
Output pin STxD is used for transmitting data. The
data is latched with the rising edge of the SCL signal.
The MSB is received first and the LSB last. Before
the STB signal, eight address bits must first be
shifted in. The STB signal sets the device into the
data mode. The MSB of the address byte defines the
read/write operation. If the MSB is high the data is
read from the device. If the MSB is low, the data is
written to the device. After the STB the written data is
DACs
Op Amps
Serial Interface
STB
SCL
STxD
STB
SCL
SRxD
STxD
SRxD
A6
A6
A5
A5
ADDRESS
ADDRESS
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
D7
D7
registers 16
size is 13 mV and the DC output level is in the range
0.3V..VDD-0.3V. The differential nonlinearity is ±0.5
LSB and the integral ±2LSB. The settling time is
10ms (max). The minimum load resistance is 30k
and the maximum load capacitance is 80pF.
TXACCOUT. The Op Amps are capable of driving
capacitive loads up to 1nF.
shifted in with the rising edge of the SCL. If the data
is to be read from the device, the STxD output is in
the state of MSB data bit after the STB signal. The
falling edge of the SCL shifts the next data bit to the
STxD output. Eight data bits must be shifted out at
which time the device exits the data mode. Because
the serial interface transmit buffer is dynamic, data
will be valid on the buffer only 200 uS after the STB
signal appears. This means that the SCL frequency
must be at least 5kHz.
D6
D6
D5
D5
HEX
D4
D4
DATA
DATA
, 17
D3
D3
HEX
D2
D2
and 18
D1
D1
HEX
D0
D0
. The typical step
DA9191A.000
July 31, 1997
R/W
R/W
21