M37220M3-010SP MITSUBISHI [Mitsubishi Electric Semiconductor], M37220M3-010SP Datasheet - Page 10

• Manufacturer Part Number: M37220M3-010SP
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER?
• Manufacturer: MITSUBISHI [Mitsubishi Electric Semiconductor]

10
INTERRUPTS
Interrupts can be caused by 13 different sources consisting of 3 ex-
ternal, 9 internal, and 1 software sources. Interrupts are vectored
interrupts with priorities shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
(2) The interrupt disable flag I is set to “1” and the corresponding
(3) The jump destination address stored in the vector address enters
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 5 shows the structure of
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 6 shows interrupt control.
Table 1. Interrupt vector addresses and priority
Reset
CRT interrupt
INT2 interrupt
INT1 interrupt
Timer 4 interrupt
X
V
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
INT3 interrupt
BRK instruction interrupt
IN
SYNC
register are automatically stored into the stack.
interrupt request bit is set to “0.”
the program counter.
/4096 interrupt
interrupt
Interrupt source
Priority
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
10
11
12
13
1
2
3
4
5
6
7
8
9
Vector addresses
FFED
FFDF
FFFD
FFEF
FFEB
FFFF
FFFB
FFE9
FFE5
FFF9
FFF5
FFF3
FFF1
16
16
16
16
16
16
16
16
16
16
16
16
16
Interrupt Causes
(1) V
(2) INT1, INT2, INT3 interrupts
(3) Timer 1, 2, 3 and 4 interrupts
(4) Serial I/O interrupt
(5) X
(6) BRK instruction interrupt
, FFFE
, FFEE
, FFDE
, FFFC
, FFFA
, FFF8
, FFF4
, FFF2
, FFF0
, FFEC
, FFEA
, FFE8
, FFE4
The V
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 5 of the interrupt input polarity register (address
00F9
tected; when it is “1,” a change from “H” to “L” is detected. Note
that all bits are cleared to “0” at reset.
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
This is an interrupt request from the clock synchronous serial
I/O function.
This interrupt occurs regularly with a f(X
of the PWM output control register 1 to “0.”
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not af-
fected by the interrupt disable flag I (non-maskable).
SYNC
IN
/4096 interrupt
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SYNC
and CRT interrupts
) : when this bit is “0,” a change from “L” to “H” is de-
interrupt is an interrupt request synchronized with
with ON-SCREEN DISPLAY CONTROLLER
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
Remarks
IN
)/4096 period. Set bit 0