HMS87C5216 ETC1 [List of Unclassifed Manufacturers], HMS87C5216 Datasheet
HMS87C5216
Related parts for HMS87C5216
HMS87C5216 Summary of contents
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... OVERVIEW 1.1 Description The HMS87C5216 is an advanced CMOS 8-bit microcontroller with 16K bytes of ROM. The device is one of GMS800 family. The Mag- naChip Semicon HMS87C5216 is a powerful microcontroller which provides a highly flexible and cost effective solution to many UR & Keyboard applications. The HMS87C5216 provides the following standard features: 16K bytes of ROM, 320 bytes of RAM, 8-bit timer/ counter, on-chip oscillator,clock circuitry and RC wake up function ...
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... HMS87C5216 1.3 Development Tools The HMS87C5216 and HMS87C5216 are supported by a full- featured macro assembler, an in-circuit emulator CHOICE Circuit Emulators CHOICE-Dr. Assembler HME Macro Assembler Single Writer : Sigma OTP Writer 4-Gang Writer : Dr.Gang OTP Devices HMS87C5216 SEP. 2004 Ver 1.01 ...
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... R14 / AN0 R24 /T2 R15 / AN1 R25 / EC0 R16 / AN2 R26 R17 / AN3 R27 REMOUT Stack Pointer Data Memory RC Watch LVD/POR Timer R3 R30 R31 R32 R33 R34 R35 R36 R37 HMS87C5216 PC Program Memory Data Table Instruction Decoder R4 R40 R41 R42 R43 R44 ...
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... HMS87C5216 3. PIN ASSIGNMENT R01 1 R02 2 R03 3 R04 4 R05 5 R06 6 R07 7 28PIN VDD 8 XOUT 9 XIN 10 R10 11 12 R11 R12 13 R13 14 R00 1 R01 2 R02 3 R03 4 R04 5 R05 6 R06 7 R07 8 R34 9 40PDIP R35 10 VDD 11 R36 12 R37 13 XOUT 14 XIN 15 R10 16 R11 17 R12 18 R13 19 R41 20 28 ...
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... PIN DIAGRAM SEP. 2004 Ver 1.01 HMS87C5216 ...
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... HMS87C5216 0.022 0.015 2.075 2.045 0.065 0.100 BSC 0.045 0.600 BSC 0.550 0.530 SEP. 2004 Ver 1.01 ...
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... SEP. 2004 Ver 1.01 HMS87C5216 ...
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... HMS87C5216 5. PIN FUNCTION V : Supply voltage Circuit ground. SS RESET: Reset the MCU Input to the inverting oscillator amplifier and input to the in- IN ternal main clock operating circuit Output from the inverting oscillator amplifier. OUT R00~R07 8-bit CMOS bidirectional I/O port. R0 pins written to the Port Direction Register can be used as outputs or inputs ...
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... Open drain output ▶Direct Driving of LED (N-TR) ▶Pull-ups are automatically disabled at output mode 1 Resetb Pin 1 Remocon Output 1 Power Supply 1 Ground HMS87C5216 @Reset @STOP Oscillation L, L State of Input before STOP State of Input before STOP State of ...
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... HMS87C5216 7. PORT STRUCTURES • RESET ll-Up Resistor Selection Open Drain Selection Direction Selection Bus MUX Noise 7:0] Canceller ll-Up Resistor Selection Open Drain Selection Direction Selection Bus MUX Noise 8 Canceller .INT2 _EN,INT2_EN VD RD Port0 KS_EN[7: Port1 KS_EN[9:8] Noise Canceller SEP. 2004 Ver 1.01 ...
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... Xin, Xout SEP. 2004 Ver 1.01 HMS87C5216 ...
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... HMS87C5216 l-Up Resistor Selection Open Drain Selection ata Register Direction Selection 0 Bus MUX Noise ,10 Canceller l-Up Resistor Selection Open Drain Selection ata Register Direction Selection Bus MUX Noise 5:12] Canceller 3:0] _EN & l-Up Resistor Selection Open Drain Selection ata Register Direction Selection Bus MUX VD RD Port1 ...
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... RA0/EC0 SEP. 2004 Ver 1.01 HMS87C5216 ...
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... HMS87C5216 ll-Up Resistor Selection Open Drain Selection Direction Selection Bus MUX _EN ll-Up Resistor Selection Open Drain Selection Direction Selection Bus MUX VDD 다단 출력 REMOUT • RA1/AN1 ~ RA7/AN7 VD RD Port2 Noise Canceller VD RD Port2,3,4 VDD PA VDD PAD XIN STOP SEP. 2004 Ver 1.01 ...
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... Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time 8.4 DC Electrical Characteristics (T =-20~85 C for HMS87C5216/1408 Parameter Symbol V Input High Voltage IH1 SEP. 2004 Ver 1.01 Note: Stresses above those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the de- vice ...
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... HMS87C5216 Parameter Symbol V IH1 Input High Voltage V IH2 V IL1 Input Low Voltage V IL2 Input High I IH Leakage Current Input Low I IL Leakage Current V OH1 Output High Voltage V OH2 V OH3 V OL1 Output Low Voltage V OL2 Output High I IOHL Leakage Current Output Low ...
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... AC Characteristics (T =-20~85 C for HMS87C5216/1408 Parameter Operating Frequency Systemp Clock Cycle Time Oscillation Stabilizing Time(4MHz) External Clock “H” or “L” Pulse Width External Clock Transition Time Interrupt Input Pulse Width RESETB Input Pulse “L” Width Event Couter Input “H” or “L” ...
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... HMS87C5216 9. MEMORY ORGANIZATION The HMS87C5216 have separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can 16K bytes of Program memory. 9.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW) ...
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... set to 1, addressing area is 1 page set by instruction and cleared by CLRG. LSB C RESET VALUE CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS ). The CLRV instruction clears the overflow flag. There H HMS87C5216 ) ...
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... HMS87C5216 9.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 16K bytes program memory space only physically implemented. Accessing a location above FFFF will cause a wrap-around to 0000 . H Figure 9-4, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in ad- ...
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... D7 D8 TCALL TCALL TCALL TCALL 0 / BRK * DF NOTE: * means that the BRK software interrupt is using same address with TCALL0. TCALL PC: NEXT 0F125H Ã 0FF00H 0FFD6H 25 0FFD7H F1 0FFFFH HMS87C5216 01001010 Reverse þ 11111111 11010110 À ...
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... HMS87C5216 Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED; (0FFEO) DW NOT_USED; (0FFE2) DW ADC_INT; (0FFE4) A/D Interface DW RC_WT_INT; (0FFE6) RC WAKE UP Timer DW BIT_INT; (0FFE8) BIT Timer DW WDT_INT; (0FFEA) WDT DW NOT_USED; (0FFEC) DW TMR2_INT; (0FFEE) Timer-2 DW TMR1_INT; (0FFF0) Timer-1 DW TMR0_INT; (0FFF2) Timer-0 DW NOT_USED ...
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... MEMORY (including STACK) 017FH Figure 9-7 Data Memory Map User Memory The HMS87C5216 has 330 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. There- ...
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... HMS87C5216 0F0H SMR W ----_---0 0F4H ADMR R/W -000_0001 0F5H ADDR R Undefined 0F6H KRL0 W 0000_0000 0F7H KRL1 W 0000_0000 0F8H R0PU W 0000_0000 0F9H R1PU W 0000_0000 0FAH R2PU W 0000_0000 0FBH R3PU W 0000_0000 0FCH R4PU W --00_0000 Table 9-1 Control Registers 1. “byte, bit” means that register can be addressed by not only bit but byte manipulation instruction. 2. “ ...
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... Addressing Mode The HMS87C5216 and GMS81C1408 uses six addressing modes; • Register addressing • Immediate addressing • Direct page addressing • Absolute addressing • Indexed addressing • Register-indirect addressing (1) Register Addressing Register addressing accesses the and PSW. (2) Immediate Addressing In this mode, second byte (operand) is accessed as a data imme- diately ...
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... HMS87C5216 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135 983500 INC !0035H 0035 data 0F100 98 þ 0F101 address: 0035 H 0F102 00 H (5) Indexed Addressing X indexed direct page (no offset) In this mode, a address is specified by the X register. ...
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... ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10 1625 JMP [35H À jump to address 0E30A ~ ~ ~ ~ 0E30A NEXT þ 0FA00 [dp+X] H ADC [25H+ À 0E005 ~ ~ ~ ~ þ 0E005 data 0FA00 HMS87C5216 X(10 Ã data + C A ...
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... HMS87C5216 Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y- register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10 H 1725 ADC [25H]+ 0E015 data 0FA00 Absolute indirect The program jumps to address specified by 16-bit absolute ad- dress ...
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... 8-bit CMOS bidirectional I/O port (address 0C2 H I/O pin can independently used as an input or an output through the R1DD register (address 0C3 Open drain select 0: Push-pull R1 has internal pull-ups that is independently connected or dis- 1: Open drain connected by register R1PC. The control registers for R1 are shown below. HMS87C5216 ). Each ...
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... HMS87C5216 R1 Data Register (R/W) R17 R16 R15 R14 R13 R12 R11 R10 R1 R1 Direction Register (W) R1DD R1 Pull-up Selection Register (W) R1PC R1 Open drain Assign Register (W) P1ODC R1 Port Mode Register (W) PMR1 (1) R1 I/O Data Direction Register (R1DD) R1 I/O Data Direction Register (R1DD) is 8-bit register, and can assign input state or output state to each bit ...
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... Open drain select lected as input. If R2PC is selected as ``1``, pull-up ia disabled 0: Push-pull and if selected as ``0``, it is enabled. R2PC is write-only register 1: Open drain and initialized as ``00 h`` in reset state. The pull-up is automati- cally disabled, if corresponding port is selected as output. HMS87C5216 ...
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... HMS87C5216 R3 Port 8-bit CMOS bidirectional I/O port (address 0E5 I/O pin can independently used as an input or an output through the R3DD register (address 0E6 ). H R3 has internal pull-ups that is independently connected or dis- connected by R3PC (address 0FB ). The control registers for R3 H are shown as below. ...
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... If R4PC is selected as ``1``, pull-up ia disabled 0: With pull-up and if selected as ``0``, it is enabled. R4PC is write-only register and initialized as ``00 h`` in reset state. The pull-up is automati- ADDRESS :0E1 H cally disabled, if corresponding port is selected as output. RESET VALUE : 00 H Open drain select 0: Push-pull 1: Open drain HMS87C5216 ...
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... HMS87C5216 11. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog OSC Circuit PRESCALER ENPCK 8 3 Peripheral CKCTLR 0 1 Figure 11-1 Block Diagram of Clock Generator Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex). The divided ...
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... KHz 7.183 KHz 128 us 3.906 KHz 3.906 KHz 256 us 1.953 KHz 1.953 KHz 512 us 0.976 KHz 0.976 KHz 1024 us 0.488 KHz Table 11-1 ps output period HMS87C5216 2 MHz period 2 MHz 500 ns 1 MHz 128 us 256 us ...
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... HMS87C5216 12. Timer 12.1 Basic Interval Timer The GMS81C5016/24/32 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 12- 1. The Basic Interval Timer generates the time base for key scan- ning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT) ...
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... PS10 (256us) is read-only register. If B.I.T register is written, then CKCTLR register with same address is written. 0 BTS2 BTS1 BTS0 W <00C7 h> Periphral clock free-run Automatically cleared, after one cycle 0 BTS2 BTS1 BTS0 W <00C7 h> Standby release time 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us HMS87C5216 ...
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... HMS87C5216 7 BIT7 BITR 12.2 Timer0, Timer1, Timer2 (1) Timer Operation Mode Timer consists of 16bit binary counter Timer0 (T0), 8bit binary Timer1 (T1), Timer2 (T2), Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 High-MSB Data Register (T0HMD), Timer0 High-LSB Data Register (T0HLD), Timer0 ...
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... T2 OUT / R15 fex = 4MHz 8bit Timer (T2) Resolution (CK) Max. Count 64 us PS5 ( 8 us) 128 us PS6 ( 16 us) 256 us PS7 ( 32 us) 512us PS8 ( 64 us) 8,192 us PS9 ( 128 us) 16,384 us PS10 ( 256 us) 32,768 us PS11 ( 512 us) 131,072 us 65,536 us PS12 (1,024 us) 262,144 us HMS87C5216 2.048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us ...
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... HMS87C5216 TM0 SINGLE/ MODULO-N SELECTION PS0 PS1 PS2 PS3 MUX PS4 PS5 PS11 EC EDGE INT2 SELECTION T0INT Figure 12-5 Block Diagram of Timer0 Internal Data Bus <00D5 h> <00D6 h> <00D0 h> TIMER0 TIMER0 H TIMER0 COUNT COUNT REG REG CK T0 COUNTER ...
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... R/W COUNT REG CK T1 COUNTER (8 BIT) Internal Data Bus <00D9 h> <00D2 h> TIMER2 R/W COUNT REG CK T2 COUNTER (8 BIT) HMS87C5216 <00D7 h> <00D8 h> TIMER1 TIMER1 H L DATA DATA REG REG OUTPUT GEN. Int. Gen. IFT1 OUTPUT GEN. T1OUT <00D9 h> TIMER2 DATA REG IFT2 OUTPUT GEN ...
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... HMS87C5216 Figure 12-7 Block Diagram of Timer2 7 TOUTS TOUTB TM01 Figure 12-8 Timer0 / Timer1 Mode Register Timer0 / Timer1 Mode Register - T0OUTP T0INIT T1INIT TOUT0 TOUT1 TOUT LOGIC 0 0 AND of T0 OUTPUT and T1 OUTPUT 0 1 NAND of T0 OUTPUT and T1 OUTPUT OUTPUT and T1 OUTPUT ...
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... Timer0 Single/Modulo-N Selection 0 Modulo-N 1 Single T0CN Timer0 Counter Continuation/Pause Control 0 Count pause 1 Count contination T0ST Timer0 Start/Stop Control 0 Timer0 Stop 1 Timer Start after clear CAP0 Timer0 Interrupt Selection 0 Timer/Counter 1 Input capture * HMS87C5216 0 T0SL1 T0SL0 <00D0 h> Notes * 1us) 2us) 4us) 8us) Event Counter ...
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... HMS87C5216 7 T1ST T1CN TM1 Figure 12-10 Timer1 Mode Register Timer1 Mode Register T1MOD T1IFS - T1SL2 T1SL2 T1SL1 T1SL0 Input clock selection PS0 (250ns PS1 (500ns PS2 ( PS3 ( PS7 ( 32us PS8 ( 64us PS9 (128us PS10 (256us) ...
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... IED2L IED1H IED Falling Edge Selection 0 Rising Edge Selection 1 Both Edge Selection 0 T2SL1 T2SL0 <00D2 h> Input clock selection PS5 ( 8us) PS6 ( 16us) PS7 ( 32us) PS8 ( 64us) PS9 ( 128us) PS10 ( 256us) PS11 ( 512us) PS12 (1024us) 0 IED1L - - W <00CB h> INT* - Register HMS87C5216 ...
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... HMS87C5216 (3) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register (TDR), T0 Data Registers Value T0 Value Figure 12-13 Operatiion of Timer0 For Timer0, the internal clock (PS) and the external clock (EC) can be selected as counter clock. But Timer1 and Timer2 use only internal clock ...
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... Stop Clear & Count Count parator and T0OUT (T1OUT ``Low``, if initial level is High? High -Data Register is transferred and to be ``High``. Sin- gle Mode can be set by Mode Select bit (T0MOD, T1MOD) of Concurrence CLEAR INTERRUPT 1 Stop Count Clear & Start continue HMS87C5216 ...
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... HMS87C5216 Timer Mode Register (TM0, TM1) to ``1`` When used as Single Mode, Timer counts up and compares with value of Data Regis- ter. If the result is same, Time Out interrupt occurs and of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD (T1MOD) should be set ``0`` ...
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... Counter Figure 12-18 Start/Stop of Timer2 SEP. 2004 Ver 1.01 Concurrence Concurrence 0 CLEAR CLEAR INTERRUPT INTERRUPT IFT0 Interval period Concurrence CLEAR INTERRUPT count stop by 0 Count Stop Count up HMS87C5216 Concurrence CLEAR INTERRUPT Concurrence CLEAR INTERRUPT count start clear by 1 Count Count up after clear continue ...
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... HMS87C5216 13. INTERRUPTS The GMS81C5016/24/32 interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Mas- ter enable flag ("I" flag of PSW). 8 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 13-1. ...
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... BITE - - INT2E - T0E T1E BITE - - INT2R - T0R T1R IMOD register. HMS87C5216 INT Vector High INT Vector Low FFFF FFFE FFFB FFFA FFF9 FFF8 FFF7 FFF6 FFF3 FFF2 FFF1 FFF0 FFEF FFEE ...
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... HMS87C5216 7 - IMOD (1) Selection of Interrupt by IP3-IP0 The condition allow for accepting interrupt is set state of the in- terrupt mask enable flag and IP3 (2) Interrupt Timing CLOCK SYNC Interrupt Request Sampling Figure 13-2 Interrupt Enable Accept Timing Interrupt Mode Register ...
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... CODE vector tion and then B flag of PSW is set and I flag is reset. -Maximum machine cycle -Minimum machine cycle ISR *1 *3 HVA new PC ↑ ``H`` vector *1 ISR : Interrupt Service Routine *2 LVA : Low Vector Address *3 HVA : High Vector Address HMS87C5216 ...
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... HMS87C5216 PSW PSW Interrupt vector of BRK instruction is shared by vector of Table Call (TCALL0). When both instruction of BRK and TCALL0 are used, as shown in Figure 13-4each processing routine is BRK or TCALL0 Figure 13-4 Execution of BRK or TCALL0 13.6 MULTIPLE INTERRUPT If there is an interrupt, Interrupt Mask Enable Flag is automatical- ly cleared before entering the Interrupt Service Routine ...
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... Key Input available). At reset, SMRR becomes ``00 h``. So, there is no Key Input source. R0 port Selection Logic R0 port Selection Logic SMRR0 Register KR06 KR05 KR04 KR03 SMRR1 Register KR16 KR15 KR14 KR13 0 W <00DC h> Internal Key Scan Interrupt 0 W <00DD h> 0 KR02 KR01 KR00 W <00DC h> 0 KR12 KR11 KR10 W <00DD h> HMS87C5216 ...
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... HMS87C5216 SMRR0 KR07 KR06 KR05 KR04 KR03 KR02 KR01 KR00 (2) Standby Release Level Control Register (SRLC) Standby release level control register (SRLC) can select the key scan input level ``L`` or ``H`` for standby release by each bit pin 7 KLR07 SRLC0 7 KLR17 SRLC1 SMRR1 ...
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... KLR16 KLR15 KLR14 KLR13 KLR12 KLR11 KLR10 1 1 HMS87C5216 Key Input Level Low High Low High Low High Low High Low High Low High Low High Low High ...
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... HMS87C5216 14. WATCH DOG TIMER Watch Dog Timer (WDT) consists of 6-bit binary counter, 6-bit 0 WDT0 IFBIT WDTR0 WDTR 0 Figure 14-1 Block diagram of Watch Dog Timer 14.1 Control of WDT Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting 7 - CKCTLR By assigning bit6(WDTCL) of WDTR, 6-bit counter can be comparator, and Watch Dog Timer Register (WDTR) ...
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... Device come into the reset state by WDT 0 WDTR1 WDTR0 W <00C8 h> (about 1second ) 0 BTS2 BTS1 BTS0 W <00C7 h> Max. Interval of WDT Output (*note1) 32,756 us 64,512 us 129,024 us 258,048 us 516,096 us 1,032,192 us 2,064,384 us 4,128,768 us HMS87C5216 ...
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... HMS87C5216 15. STANDBY FUNCTION To save power consumption, there is STOP modes. In this modes, 15.1 Sleep Mode SLEEP mode can be entered by setting the bit of SLEEP mode register (SLPM). In the mode, CPU clock stops but oscillator keeps running. B.I.T and a part of peripheral hardware execute, but prescalerís output which provide clock to peripherals can be stopped by program. (Except, PS10 caní ...
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... Figure 15-2 ENPCK and Basic Interval Timer Clock SEP. 2004 Ver 1.01 OSC. Clock Pulse GEN Circuit CLR MUX Prescaler CLR Release Signal From Interrupt Circuit RESET Prescaler PS10 Selector CPU Clock B.I.T 7 Basic Interval Timer CLR Overflow Detection Basic Interval Timer HMS87C5216 ...
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... HMS87C5216 15.3 STANDBY MODE RELEASE Release of STANDBY mode is executed by RESET input and In- terrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET input), the Release Signal RESET KSCN (key input) INT1 , INT2 B.I.T Release Factor RESET KSCN ...
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... B.I.T. otherwise, standby mode is released by reset signal. In case of interrupt re- quest flag and interrupt enable flag are both ``1``, standby mode is not entered. Longer than 2 machine cycle Stable STOP Mode OSC. time Program Setting Time by CKCTLR Longer than stable OSC. Time HMS87C5216 ...
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... HMS87C5216 Interrupt Service Routine Figure 15-4 Standby Mode Release Flow Internal circuit Oscillator Internal CPU clock Register RAM I/O port Prescaler Basic Interval Timer Watch Dog Timer Timer Address Bus, Data Bus STOP Command Standby Mode Interrupt Request GEN Flag 1 Standby Mode Release ...
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... In the Standby (STOP) mode, oscillatiion stop, Xout state goes to ``HIigh``, Xin state goes to ``Low``, and built-in feed back resistor is disabled. Cout Cin External clock Part Name CQ ZTA4.00MG TDK FCR4.0MC5 TDK FCR4.0M5 TDK CCR4.0MC3 Load Capacitor Operating Voltage Cin=Cout=30pF 2.2 ~ 4.0V Cin=Cout=open 2.2 ~ 4.0V Cin=Cout=33pF 2.2 ~ 4.0V 2.2 ~ 4.0V HMS87C5216 ...
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... HMS87C5216 17. RESET FUNCTION 17.1 EXTERNAL RESET The RESET pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uF capacitor for stable system initial- Figure 17-1 17.2 POWER ON RESET Power On Reset circuit automatically detects the rise of power ...
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... Release of Low Voltage Detection Mode Reset signal result from new battery(normally 3V) wakes the low voltage detection mode and come into normal reset state. It de- pends on user whether to execute RAM clear routine or not. HMS87C5216 FFFE FFFF NEW PC LSB MSB VECTOR ...
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... HMS87C5216 Figure 17-5 Low Voltage vs Temperature (4) SRAM BACK-UP after Low Voltage Detection. 3.0V MCU OPR. Voltage 1.8V(TYP) ( 20℃) 0.7V(V ) RET 0V User Removes Batteries Figure 17-6 Low Voltage Detection and Protection Low Voltage (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0℃ 10℃ 20℃ 30℃ Temperature(℃) about hours depend on Vcc-Gnd Capacitor Low Voltage Detection ...
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... VDD level sequentially. The VDD dection levels for Indication are two , that is , Bit1 and Bit0 of LVIR Register. The detection level of Bit0 is higer than Bit1 Clear All Ram area LVIR1 LVIR0 <00EF h> HMS87C5216 ...
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... HMS87C5216 18. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog OSC Circuit PRESCALER ENPCK 8 3 Peripheral CKCTLR 0 1 Figure 18-1 Block Diagram of Clock Generator Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex). The divided ...
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... The HMS87C5216 and GMS81C1408 has one 8-bit Basic Inter- val Timer that is free-run, can not stop. Block diagram is shown in Figure 18-3.The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescal- er. Since prescaler has divided ratio 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency ...
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... HMS87C5216 Clock Control Register CKCTLR - WAKEUP RCWDT Symbol 1 : Enables Wake-up Timer WAKEUP 0 : Disables Wake-up Timer 1 : Enables Internal RC Watchdog Timer RCWDT 0 : Disables Internal RC Watchdog Time 1 : Enables Watchdog Timer WDTON 0 : Operates as a 7-bit Timer 1 : BITR is cleared and BTCL becomes “0” automatically BTCL ...
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... A/D conversion is completed, cleared when A/D conver- sion is in process. The conversion time takes maximum 30 uS (at fxin=4 MHz). ADAN[1:0] 11 Sample & Hold S Resistor 00 Ladder Circuit Figure 19-1 A/D Converter Block Diagram HMS87C5216 A/D Result Register ADDRESS : EDH ADDR(8-bit) RESET VALUE : Undefined Successive ADIF Approximation Circuit A/D Interrupt ...
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... HMS87C5216 A/D Control Register ADMR - ANEN A/D Result Data Register ADCR ADCR7 ADCR6 ENABLE A/D CONVERTER A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT A/D START (ADST = 1) NOP ADSF = 1 YES READ ADCR Figure 19-3 A/D Converter Operation Flow ADAN3 ADAN2 ADAN1 ADAN0 Analog Channel Select 0000 : Channel 0 (R1[4]/AN0) 0001 : Channel 1 (R1[5]/AN1) ...
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... Also, if digital pulses are applied to a pin adjacent to the pin in the SEP. 2004 Ver 1.01 process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid ap- plying pulses to pins adjacent to the pin undergoing A/D conver- sion. HMS87C5216 ...
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... HMS87C5216 SEP. 2004 Ver 1.01 ...