EM78159NAS EMC [ELAN Microelectronics Corp], EM78159NAS Datasheet - Page 29

• Manufacturer Part Number: EM78159NAS
• Description: 8-Bit Microcontroller with OTP ROM
• Manufacturer: EMC [ELAN Microelectronics Corp]

Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
4.6 Interrupt
The EM78P159N has three falling-edge interrupts as listed herewith:
1) TCC overflow interrupt
2) Port 6 Input Status Change Interrupt
3) External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV
R6,R6") is necessary. Each Port 6 pin will have this feature if its status changes. Any
pin configured as output or P60 pin configured as /INT is excluded from this function.
The Port 6 Input Status Changed Interrupt can wake up the EM78P159N from Sleep
mode if Port 6 is enabled prior to going into the Sleep mode by executing SLEP. When
the chip wakes-up, the controller will continue to execute the succeeding address if the
global interrupt is disabled or it will branch into the interrupt vector 008H if the global
interrupt is enabled.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of RF will be the
logic AND of RF and IOCF (refer to figure below). The RETI instruction ends the
interrupt routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from Address 001H.
/IR Q n
V C C
/R E S E T
D
R F
C L K
P
R
C
L
Q
Q
_
Figure 4-7 Interrupt Input Circuit
IO C F
Q
Q
_
IO C F R D
R F W R
P
R
C
L
C L K
D
R F R D
IO C F W R
8-Bit Microcontroller with OTP ROM
IR Q n
IR Q m
IO D
E N I/D IS I
EM78P159N
IN T
• 25