IW4029BD IKSEMICON [IK Semicon Co., Ltd], IW4029BD Datasheet

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IW4029BD

Manufacturer Part Number
IW4029BD
Description
Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS
Manufacturer
IKSEMICON [IK Semicon Co., Ltd]
Datasheet
TECHNICAL DATA
Presettable Up/Down Counter
High-Voltage Silicon-Gate CMOS
counter with provisions for look-ahead carry in both counting modes. The
inputs consists of a single CLOCK, CARRY IN,(CLOCK ENABLE),
BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as
outputs.
INPUTS to preset the counter to any state asynchronously with the clock.
A low on each JAM line, when the PRESET-ENABLE signal is high,
resets the counter to its zero count. The counter is advanced one count at
the positive transition of the clock when the CARRY IN and PRESET
ENABLE signals are low. Advancement is inhibited when the
CARRY IN or PRESET ENABLE signals are high. The CARRY OUT
signal is normally high and goes low when the counter reaches its
maximum count in the UP mode or the minimum count in the DOWN
mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK
ENABLE. The CARRY IN terminal must be connected to GND when
not in use.
input is high; the counter counts in the decade mode when the
BINARY/DECADE input is low. The counter counts up when the
UP/DOWN input is high, and down when the UP/DOWN input is low.
response from all counting outputs. Ripple-clocking allows for longer
clock input rise and fall times.
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 μA at 18 V over full package-
• Noise margin (over full package temperature range):
The IW4029B consists of a four-stage binary or BCD-decade up/down
A high PRESET ENABLE signal allows information on the JAM
Binary counting is accomplished when the BINARY/DECADE
Parallel clocking provides synchronous control and hence faster
temperature range; 100 nA at 18 V and 25°C
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
LOGIC DIAGRAM
PIN 16=V
PIN 8= GND
T
A
ORDERING INFORMATION
= -55° to 125° C for all packages
PIN ASSIGNMENT
CC
IW4029BN Plastic
IW4029BD SOIC
IW4029B
Rev. 00

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IW4029BD Summary of contents

Page 1

... V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION T = -55° to 125° C for all packages A PIN ASSIGNMENT LOGIC DIAGRAM PIN 16=V CC PIN 8= GND IW4029B IW4029BN Plastic IW4029BD SOIC Rev. 00 ...

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MAXIMUM RATINGS Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin IN P Power Dissipation in Still ...

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DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage V Maximum Low - IL Level Input Voltage V Minimum High-Level OH Output Voltage V Maximum Low-Level OL Output Voltage I Maximum Input IN Leakage Current I Maximum Quiescent ...

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AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Maximum Clock Frequency (Figure 1) max Maximum Propagation Delay, Clock to Q PHL PLH (Figure Maximum Propagation Delay, Clock to Carry PHL PLH Output (Figure 1) t ...

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TIMING REQUIREMENTS (C Symbol Parameter t Minimum Pulse Width, Clock (Figure Minimum Pulse Width, Preset Enable w (Figure Minimum Setup Time, Clock to B/D or U/D su (Figure Minimum Removal Time, ...

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Figure 1. Switching Waveforms Figure 2. Switching Waveforms IW4029B Rev. 00 ...

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TIMING DIAGRAM; binary mode; J1=HIGH; J2=LOW; BIN/DEC=HIGH TIMING DIAGRAM; decade mode; J1=LOW; J4=LOW; BIN/DEC=LOW IW4029B Rev. 00 ...

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IW4029B EXPANDED LOGIC DIAGRAM TRUTH TABLE CLOCK ...

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- 0.25 (0.010 NOTES: 1. imensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. A ...

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