MX29LV065TC-12 MCNIX [Macronix International], MX29LV065TC-12 Datasheet
MX29LV065TC-12
Related parts for MX29LV065TC-12
MX29LV065TC-12 Summary of contents
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FEATURES GENERAL FEATURES • 8,388,608 x 8 byte structure • One hundred twenty-eight Equal Sectors with 32K byte each - Any combination of sectors can be erased with erase suspend/resume function • Sector Protection/Chip Unprotected - Provides sector group protect ...
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The MX29LV065 uses a command register to manage this functionality. MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and ...
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PIN CONFIGURATION 48 TSOP NC 1 A22 2 A16 3 A15 4 A14 5 A13 6 A12 7 A11 RESET RY/BY 14 A18 ...
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PIN DESCRIPTION SYMBOL PIN NAME A0~A22 Address Input Q0~Q7 8 Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input RESET Hardware Reset Pin, Active Low RY/BY Read/Busy Output VCC +3.0V single power supply VI/O Input/Output ...
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BLOCK DIAGRAM CONTROL CE INPUT OE LOGIC WE ADDRESS LATCH A0-A22 AND BUFFER Q0-Q7 P/N:PM0893 MX29LV065 PROGRAM/ERASE HIGH VOLTAGE MX29LV065 FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 5 WRITE STATE ...
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SECTOR (GROUP) STRUCTURE Sector A22 A21 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 0 SA8 0 0 SA9 0 0 SA10 0 0 SA11 ...
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Sector A22 A21 SA38 0 1 SA39 0 1 SA40 0 1 SA41 0 1 SA42 0 1 SA43 0 1 SA44 0 1 SA45 0 1 SA46 0 1 SA47 0 1 SA48 0 1 SA49 0 1 SA50 ...
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Sector A22 A21 SA78 1 0 SA79 1 0 SA80 1 0 SA81 1 0 SA82 1 0 SA83 1 0 SA84 1 0 SA85 1 0 SA86 1 0 SA87 1 0 SA88 1 0 SA89 1 0 SA90 ...
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Sectpr A21 A20 SA118 1 1 SA119 1 1 SA120 1 1 SA121 1 1 SA122 1 1 SA123 1 1 SA124 1 1 SA125 1 1 SA126 1 1 SA127 1 1 Note: All sector groups are 64K bytes ...
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Sector Group Protection/Unprotected Address Table Sector Group A21-A17 SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 SA64-SA67 SA68-SA71 SA72-SA75 SA76-SA79 SA80-SA83 SA84-SA87 SA88-SA91 SA92-SA95 SA96-SA99 SA100-SA103 SA104-SA107 SA108-SA111 SA112-SA115 SA116-SA119 SA120-SA123 SA124-SA127 ...
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Table 1 BUS OPERATION (1) Operation CE Read L Write (Program/Erase) L Standby VCC±0.3V Output Disable L Reset X Sector Group Protect L (Note 1) Sector Group L Unprotected (Note 1) Temporary Sector Group X Unprotected Legend: L=Logic LOW=V ,H=Logic ...
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AUTO-SELECT CODES (High Voltage Method) Operation Read Silicon Manufactures Code Read Silicon Device Code Sector Protect Verify L L Secured Silicon Sector Indicator Bit(Q7 Notes: 1.code=00h means unprotected, or ...
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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE and OE pins to VIL the power control and selects the device the output control and gates array ...
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OUTPUT DISABLE With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins high impedance state. RESET OPERATION The RESET pin provides a hardware method ...
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TEMPORARY SECTOR GROUP UNPRO- TECTED OPERATION This feature allows temporary unprotected of previously protected sector to change data in-system. The Tempo- rary Sector Unprotected mode is ...
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VERIFY SECTOR GROUP PROTECT STATUS OPERATION MX29LV065 provides hardware method for sector group protect status verify. Which method requires VID on A9 pin, VIH on WE and A1 pins, VIL on CE, OE, A6, and A0 pins, and sector address ...
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LOW VCC WRITE INHIBIT When VCC is less than VLKO the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device ...
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SOFTWARE COMMAND DEFINITIONS Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. ...
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Notes: 1. See Table 1 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and fourth cycle of the auto-select command sequence, all bus cycles are write cycles. 4. Unless otherwise noted, ...
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This method is an alternative to that shown in Table 1, which is intended for PROM programmers and requires V on address bit A9. ID The SILICON ID READ command sequence is initiated by writing two unlock cycles, followed by ...
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SETUP AUTOMATIC CHIP/SECTOR ERASE Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H, ...
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WE or CE, whichever happens first. Sector addresses selected are loaded into internal register on the sixth falling edge CE, whichever happens later. Each ...
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Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set ...
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Table 4-3. CFI Mode: Device Geometry Data Values Description Device size (2 n bytes) Flash device interface code (02=asynchronous x8/x16) Maximum number of bytes in multi-byte write (not supported) Number of erase block regions Erase block region 1 information [2E,2D] ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY. Table 10 and the following subsections describe the func- tions of these bits. Q7, RY/BY, and Q6 ...
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Q7: Data Polling The Data Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. Data Polling is valid after the rising edge of ...
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But Q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. Q6, by com- parison, indicates whether the device is actively eras- ing Erase Suspend, but cannot distinguish which sectors are selected for erasure. ...
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high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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DC CHARACTERISTICS TA=-40° ° ° ° ° 85° ° ° ° ° C, VCC=2.7V~3.6V Para- meter Description I LI Input Load Current (Note 1) I LIT A9 Input Load Current I LO Output Leakage Current ICC1 VCC Active ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST CL 6.2K ohm KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Don't Care, Any Change Permitted Does Not Apply SWITCHING TEST WAVEFORMS 3.0V 0.0V INPUT P/N:PM0893 TEST SPECIFICATIONS Test Condition Output Load 2.7K ohm Output Load ...
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AC CHARACTERISTICS Read-Only Operations TA=-40° ° ° ° ° 85° ° ° ° ° C, VCC=2.7V~3.6V Parameter Std. Description tRC Read Cycle Time (Note 1) tACC Address to Output Delay tCE Chip Enable to Output Delay tOE Output ...
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Fig 1. COMMAND WRITE OPERATION VCC 5V VIH Addresses VIL tAS VIH WE VIL tOES CE VIH VIL tCS OE VIH VIL VIH Data VIL READ/RESET OPERATION Fig 2. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE VIL VIH WE ...
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AC CHARACTERISTICS Parameter Description tREADY1 RESET PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP RESET Pulse Width (NOT During Automatic Algorithms) tRH ...
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ERASE/PROGRAM OPERATION Fig 4. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC xxxh Address CE OE tWP WE tCS tDS tDH Data RY/BY tVCS VCC NOTES: 1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write ...
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Fig 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM0893 START Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 80H Address XXXH Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 10H Address XXXH Data ...
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Fig 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM0893 START Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 80H Address XXXH Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data 30H Sector Address NO ...
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Fig 7. ERASE SUSPEND/RESUME FLOWCHART P/N:PM0893 START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another NO Erase ...
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Fig 8. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART Device Failed P/N:PM0893 MX29LV065 START Enter Secured Silicon Sector Wait 1us First Wait Cycle Data=60h Second Wait Cycle Data=60h A6=0, A1=1, A0=0 Wait 300us No Data = 01h ? Yes Write Reset ...
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AC CHARACTERISTICS Erase and Program Operations TA=-40° ° ° ° ° 85° ° ° ° ° C, VCC=2.7V~3.6V Parameter Std. Description tWC Write Cycle Time (Note 1) tAS Address Setup Time tASO Address Setup Time to OE low ...
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Fig 9. AUTOMATIC PROGRAM TIMING WAVEFORMS Program Command Sequence(last two cycle) tWC XXXh Address CE OE tWP WE tCS tDS tDH Data RY/BY tVCS VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address P/N:PM0893 Read ...
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AC CHARACTERISTICS Alternate CE Controlled Erase and Program Operations Parameter Std. Description tWC Write Cycle Time (Note 1) tAS Address Setup Time tAH Address Hold Time tDS Data Setup Time tDH Data Hold Time tGHEL Read Recovery Time Before Write ...
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Fig 10. CE CONTROLLED PROGRAM TIMING WAVEFORM XXX for program XXX for erase Address tWC tWH WE tGHEL OE tCP CE tWS tDS Data tRH RESET RY/BY NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. ...
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Fig 11. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM0893 MX29LV065 START Write Data AAH Address XXXH Write Data 55H Address XXXH Write Data A0H Address XXXH Write Program Data/Address Data Poll from system No Verify Byte Ok ? YES No ...
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SECTOR GROUP PROTECT/CHIP UNPROTECTED Fig 12. Sector Group Protect / Protect and Unprotected Waveform (RESET Control) VID VIH RESET SA, A6 A1, A0 Sector Group Protect or Chip Unprotect Data 60h 1us Note: For sector group protect ...
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Fig 13. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECTED ALGORITHMS WITH RESET=VID START PLSCNT=1 RESET=VID Wait 1us No First Write Temporary Sector Unprotect Mode Cycle=60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait ...
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Fig 14. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE Control 12V 3V A9 tVLHT 12V 3V OE tVLHT WE CE Data A21-A16 P/N:PM0893 tWPP 1 tOESP Sector Address 47 MX29LV065 Verify tVLHT 01H F0H tOE REV. 0.4, JUL. ...
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Fig 15. SECTOR GROUP PROTECTION ALGORITHM (A9, OE Control) No PLSCNT=32? Yes Device Failed P/N:PM0893 START Set Up Sector Addr PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 150us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector Addr=SA, ...
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Fig 16. CHIP UNPROTECTED TIMING WAVEFORM (A9, OE Control) A1 12V 3V A9 tVLHT A6 12V 3V OE tVLHT WE CE Data P/N:PM0893 tVLHT tWPP 2 tOESP 49 MX29LV065 Verify 00H F0H tOE REV. 0.4, JUL. 22, 2003 ...
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Fig 17. CHIP UNPROTECTED FLOWCHART (A9, OE Control) Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0893 START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out ...
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AC CHARACTERISTICS Parameter Description tVIDR VID Rise and Fall Time (see Note) tRSP RESET Setup Time for Temporary Sector Unprotected tRRB RESET Hold Time from RY/BY High for Temporary Sector Group Unprotected Fig 18. TEMPORARY SECTOR GROUP UNPROTECTED WAVEFORMS 12V ...
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Fig 19. TEMPORARY SECTOR GROUP UNPROTECTED FLOWCHART Temporary Sector Unprotect Completed(Note 2) Note : 1. All protected sectors are temporary unprotected. P/N:PM0893 Start RESET = VID (Note 1) Perform Erase or Program Operation Operation Completed RESET = VIH VID=11.5V~12.5V 2. ...
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Fig 20. SILICON ID READ TIMING WAVEFORM VCC 5V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC A1 VIH VIL VIH ADD VIL CE VIH VIL tCE VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N:PM0893 ...
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WRITE OPERATION STATUS Fig 21. DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE tCH tOE OE tOEH WE Q7 Q0-Q6 tBUSY RY/BY NOTES: VA=Valid address. Figure shows are first status cycle after command sequence, last ...
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Fig 22. Data Polling Algorithm No Notes: 1.VA=valid address for programming. 2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM0893 Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes ...
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Fig 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE tCH tOE OE tOEH WE tDH Q6/Q2 Valid Status RY/BY NOTES: VA=Valid address; not required for Q6. Figure shows first two status cycle after command ...
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Fig 24. Toggle Bit Algorithm NO Note: 1.Read toggle bit twice to determine whether or not it is toggling. 2.Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM0893 START Read Q7~Q0 Read Q7~Q0 (Note 1) ...
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Fig 25. Q6 versus Q2 Enter Embedded Erase Erasing Suspend Erase NOTES: The system can use toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM0893 Enter Erase Suspend ...
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ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1. Not 100% Tested, Excludes external system level over head. 2. Typical program and erase times assume the following ...
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... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX29LV065TC-90 90 MX29LV065TC-12 120 MX29LV065XBC-90 90 MX29LV065XBC-12 120 MX29LV065TI-90 90 MX29LV065TI-12 120 MX29LV065XBI-90 90 MX29LV065XBI-12 120 P/N:PM0893 MX29LV065 Ball Pitch/ PACKAGE Ball size 48 Pin TSOP (Normal Type) 48 Pin TSOP (Normal Type) 0.8mm/0.3mm 63 Ball CSP 0.8mm/0.3mm 63 Ball CSP ...
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PACKAGE INFORMATION P/N:PM0893 MX29LV065 61 REV. 0.4, JUL. 22, 2003 ...
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P/N:PM0893 MX29LV065 62 REV. 0.4, JUL. 22, 2003 ...
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REVISION HISTORY Revision # Description 0 correct the type error 2. To modify package/ordering information 3. Removed 100ns speed information 0 modify Package Information 0.3 1. Removed ACC function and relate information 2. Removed unlock bypass ...
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