R8800I RDC [RDC Semiconductor], R8800I Datasheet - Page 2

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R8800I

Manufacturer Part Number
R8800I
Description
16-BIT RISC MICROCONTROLLER
Manufacturer
RDC [RDC Semiconductor]
Datasheet
R
1.
l CPU Core
l Bus Interface
l ROM/RAM Controller and Addressing Space
l PSRAM Interface
l Two Independent DMA Channels
l Asynchronous Serial Channel
l Interrupt Controller
Specifications subject to change without notice, contact your sales representatives for the most update information.
R
- RDC’s proprietary RISC architecture
- Five-stage pipeline
- CPU clock speed up to 25 MHz
- Supports CPU ID
- Supports 32 PIO pins
- Static & synthesizable design
- A multiplexed address and data bus which is
- Supports a non-multiplexed address bus A[19:0]
- 1M-byte memory address space
- 64K-byte I/O space
- PSRAM (Pseudo static RAM) interface with
- Supports one asynchronous serial channel with
compatible with the 80C188 microprocessor
auto-refresh control
one synchronous serial channel
Features
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l Programmable Chip-select Logic
l Programmable Wait-state Generator
l Counter/Timers
l Software compatible with the 80C188
l Operating Voltage Range
l Ambient Temperature: -40 ~ +85°C
l Package Type
- The Interrupt controller with five maskable
- Programmable chip-select logic for memory or I/O
- 3 independent 16-bit timers and Timer 1 can be
- Core voltage: 5V ± 5%
- I/O voltage: 5V ± 10%
- 100-pin PQFP
- 100-pin LQFP
microprocessor
external interrupts and 1 non-maskable external
interrupt
bus cycle decoder
programmed as a watchdog timer
16-BIT RISC MICROCONTROLLER
REV 1.0 Oct.26 2006
R8800I

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