R1120 RDC [RDC Semiconductor], R1120 Datasheet - Page 2

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R1120

Manufacturer Part Number
R1120
Description
16-BIT RISC MICROCONTROLLER
Manufacturer
RDC [RDC Semiconductor]
Datasheet

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1.
Specifications subject to change without notice, contact your sales representatives for the most update information.
R
Five-stage pipeline
RISC architecture
Integrated PLL (*1~*8)
Maximum frequency: 80 MHz; the external bus,
internal bus and core are operating in the same
clock base
Static & synthesizable design
Bus interface
- A multiplexed address and data bus which is
- Supports a direct address bus A[19:0]
- 1M-byte memory address space
- 64K-byte I/O space
Software is compatible with the 80C186
microprocessor
Supports two asynchronous serial channels with
hardware handshaking signals
Supports CPU ID
Supports 32 PIO pins
compatible with the 80C186 microprocessor
Features
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Page 2 of 5
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PSRAM (Pseudo static RAM) interface with auto-refresh
control
Three independent 16-bit timers and one independent
watchdog timer
The Interrupt controller with seven maskable
external interrupts and one non-maskable external
interrupt
Two independent DMA channels
Programmable chip-select logic for memory or I/O
bus cycle decoder
Programmable wait-state generators
The I/O pin output is 3.3 volt level and the input
3.3 to 5 volt tolerance.
3.3V operation voltage
Supports serial port/ DMA transfers
With 8-bit or 16-bit boot ROM bus size
A green product
- PQFP100 pins & LQFP100 pins
16-BIT RISC MICROCONTROLLER
REV 1.0 Jul. 28 2005
R1120

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